Zhengwen Li

A 0.039um 2 high performance eDRAM cell based on 32nm High-K/Metal SOI technology

We present industrys smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The cell is aggressively scaled at 58% (vs. 45nm) and features the key innovation of High-K Metal (HK/M) stack in the Deep Trench (DT) capacitor. This has enabled 25% higher capacitance and 70% lower resistance compared to conventional SiON/Poly stack at matched leakage and reliability. The HKMG access transistor developed in high performance optimized technology features sub 3fA leakage and well-controlled threshold voltage sigma of 40mV. The fully integrated 32Mb product prototypes demonstrate state of the art performance with excellent retention and yield characteristics. The sub 1.5ns latency and 2ns cycle time have been verified with preliminary testing whereas even better performance is expected with further characterization. In addition, the trench capacitors set the industry benchmark for the most efficient decoupling in any 32nm technology.

A novel atomic layer oxidation technique for EOT scaling in gate-last high-к/metal gate CMOS technology

We demonstrated sub-1nm equivalent oxide thickness (EOT) for a gate-last high- к/metal scheme. This is enabled by (1) controllable 1000°C high temperature atomic layer oxidation on a chemical oxide (chemox) to form < 0.5 nm high quality SiO2 interfacial layer (IL); (2) nitrogen profile optimization on post high- к nitridation and anneal. Competitive gate leakage and mobility are achieved at the scaled EOT compared to a chemox IL control (0.2 nm thinner). The physical properties of the gate stack are studied by XPS and SIMS analysis.

Replacement metal gate resistance in FinFET architecture modelling, validation and extendibility

In this paper, we develop a multiplicative model to simulate the tungsten (W) film resistivity and gate resistance for replacement metal gate (RMG) with W electrode. Our multiplicative model predicts that TiN fill offers the lower gate resistance than TiN/W fill for highly scaled gate lengths. By absorbing the results from our model into the real RMG FinFET devices, we observe that TiN fill provides ~6.4 % performance improvement compared to TiN/W fill. Meanwhile, the employment of gate conductance for gate stack film thickness monitoring is also described in our work.