Chenyun Pan

A Paradigm Shift in Local Interconnect Technology Design in the Era of Nanoscale Multigate and Gate-All-Around Devices

As the technology scales down to the sub-10 nm nodes, the interconnect performance becomes primarily dominated by the resistance rather than the capacitance due to the ever-increasing size effects of copper and a higher input capacitance of the devices. The implications of this paradigm shift are discussed in this letter, and it is shown that the local interconnect technology needs to be reoptimized to rebalance the interconnect resistance and capacitance. One approach is to increase the interconnect width beyond half pitch without changing the interconnect pitch. For the 5-nm technology node with an aspect ratio of 3, the energy-delay product of vertical field-effect transistor circuits at the optimal relative width improve up 55%, compared with the circuits using an aspect ratio of 2 and an interconnect width of half pitch.

Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moores Law. For the first time, the performance of two GAA device options- lateral FET (LFET) and vertical FET (VFET)-is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi-Vth optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power.

Device- and system-level performance modeling for graphene P-N junction logic

Based on the property of angular dependent transmission probability of electrons observed in graphene PN junctions, a modified MUX-based graphene logic device is introduced. A more elaborate resistance model including ON resistance, leakage resistance and contact resistance is given as well as a capacitance model of the device. Compared with Si CMOS switches, MUX-based logic graphene gates have potentially lower output resistances and a smaller device area. Since interconnects play an ever increasing important role in digital circuit, for the first time, module-level and system-level analyses are made for better evaluating the potential performance of graphene logic devices. Based on the analysis of a 32-bit Han-Carlson adder, module-level evaluation has been done and comparison has been made between graphene logic circuits complemented by multilayer graphene interconnects and CMOS logic circuits with Cu/low k interconnects. The results indicate that MUX-based graphene logic circuits can outperform CMOS circuits in terms of both delay and power consumption. Both devices being evaluated are based on the 15nm technology node. For the system-level analysis, the graphene logic system can have 50% higher throughput than its Si CMOS counterpart with the same power density and die size area.

A Proposal for a Novel Hybrid Interconnect Technology for the End of Roadmap

To suppress the impact of size effects on sub-20 nm wide wires, a novel aluminum-copper hybrid interconnect architecture is proposed and its potential performance has been quantified. Al wires offer lower resistivities at nanoscale dimensions because they do not need diffusion barriers, and size effects are less prominent in them due to their smaller bulk mean free path. However, their current conduction capacity is substantially lower than that of Cu wires. To get around this limitation, this letter proposes a hybrid interconnect technology to replace only short narrow local signal wires by Al wires. This scheme takes advantage of the fact that signal wires conduct bi-directional currents and are therefore virtually immune to electromigration. The improvement in chip clock frequency is predicted to be between 50% and 100% for the 7 nm technology node.

A Proposal for Energy-Efficient Cellular Neural Network Based on Spintronic Devices

Due to the massive parallel computing capability and outstanding image and signal processing performance, cellular neural network (CNN) is one promising type of non-Boolean computing system that can outperform the traditional digital logic computation and mitigate the physical scaling limit of the conventional CMOS technology. The CNN was originally implemented by VLSI analog technologies with operational amplifiers and operational transconductance amplifiers as neurons and synapses, respectively, which are power and area consuming. In this paper, we propose a hybrid structure to implement the CNN with magnetic components and CMOS peripherals with a complete driving and sensing circuitry. In addition, we propose a digitally programmable magnetic synapse that can achieve both positive and negative values of the templates. After rigorous performance analyses and comparisons, optimal energy is achieved based on various design parameters, including the driving voltage and the CMOS driving size. At a comparable footprint area and operation speed, a spintronic CNN is projected to achieve about one order of magnitude energy reduction per operation compared to its CMOS counterpart.

Technology/Circuit/System Co-Optimization and Benchmarking for Multilayer Graphene Interconnects at Sub-10-nm Technology Node

Based on realistic circuit- and system-level simulations, graphene interconnects are analyzed in terms of multiple material properties, such as the mean free path (MFP), the contact resistance, and the edge roughness. The benchmarking results indicate that the advantage of using graphene interconnects occurs only under certain circumstances. The device-level parameters, including the supply and threshold voltages, and the circuit-level parameters, including the wire length and width, have large impacts on both the delay and energy-delay product (EDP). At the circuit level, one representative circuit, a 32-bit adder, is investigated, where up to 40% and 70% improvements in delay and EDP are observed. At the system-level analysis, an ARM Cortex-M0 processor is synthesized, and placement and routing are performed. After replacing copper interconnects with multilayer graphene interconnects, up to 15% and 22% performance improvements in clock frequency and EDP have been observed. It is also demonstrated that the benefits of using graphene for the ARM core processor are strongly dependent on the quality of the graphene, such as the MFP and the edge roughness.

BEOL Scaling Limits and Next Generation Technology Prospects

This paper presents the major limitations to the interconnect technology scaling at future technology generations and demonstrates both evolutionary and radical potential solutions to the BEOL scaling problem. To address the local interconnect challenges, a novel hybrid Al-Cu interconnect technology is introduced. Performances of carbon-based interconnects are evaluated as a more radical solution. The impact of interconnects and the optimal interconnect options are investigated for emerging next generation devices. Interconnects for new state variables, namely spintronic interconnects, are studied and their potential performances in an all-spin logic system are evaluated.

Interconnect Design and Benchmarking for Charge-Based Beyond-CMOS Device Proposals

This letter presents a uniform interconnect-centric benchmark methodology for various emerging charge-based device technologies, including ferroelectric FETs, tunneling FETs, piezoelectric FET, graphene pn junction, and 2D material-based FET. Multiple key metrics are proposed and implemented to quantify the circuit/system limitations imposed by repeaters and interconnects. The results in this letter give device technologists an insightful perspective to better balance and manage the trade-offs of intrinsic device properties for the optimum interconnect performance.

Adapting Interconnect Technology to Multigate Transistors for Optimum Performance

Beyond the 22-nm technology node, interconnect parasitics are increasingly contributing to the degradation of circuit performance. Thus, the focus is on optimizing interconnect parasitics in order to achieve optimum performance. The increased total device capacitance and the reduced device resistance of multigate transistors amplify the importance of wire resistance in circuit delay. In this paper, the impact of interconnect resistance on the circuit performance is weighed against interconnect capacitance, and less aggressive wire width and thickness scaling are proposed. This analysis is carried out based on the results from fully timing-closed, GDSII-level layout of circuit blocks, for the 11- and 7-nm technology nodes. The sensitivity of circuit power dissipation and signal noise to interconnect dimensions is assessed in detail. This approach compromises wire capacitance and gradually renders it important in circuit delay. The circuit performance enhancement by air-gap (AG) interconnect technology is studied with the traditional BEOL scaling versus the proposed wire sizing. It is found that using the latter wire sizing approach with air-gap interconnects is more beneficial to circuit performance.

System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model

Many novel devices are being pursued in recent years to augment or even replace CMOS technology. It is, therefore, important to develop a methodology to effectively evaluate the system-level performance of the emerging technologies. In this paper, an empirical cycles per instruction (CPI) model is presented based on Intel microprocessor family, which can be utilized to quantify the chip throughput for an emerging device technology at the early stage of technology development without detailed design and optimization of a full processor. Graphene pn junction devices are used as a platform for the proposed methodology. It is demonstrated that for the same power density and die size area, the maximum throughput of an optimized graphene logic single-core system can be 35% higher than that of its CMOS counterpart at 15nm technology node.