Ahmet Ceyhan

Cu Interconnect Limitations and Opportunities for SWNT Interconnects at the End of the Roadmap

The historical understanding of the interconnect problem in electronics has been that the penalty due to the performance degradation of interconnects with technology scaling would be most severe for long interconnects at the global level. At the nanoscale, however, the nature of the interconnect problem changes and paves the way for new opportunities. This is because of the fact that the metal resistivity at small interconnect dimensions drastically increases due to size effects. In this paper, it is shown that the historical trend of achieving smaller interconnect latency for short local- and intermediate-level interconnects will not hold true for future technology nodes. This paper investigates new opportunities that rise as a consequence of this radical change in the nature of the interconnect problem. Contrary to the previous publications, which have indicated that individual single-wall carbon nanotube (SWNT) interconnects are too resistive for high-performance CMOS applications and must be used in bundles, this paper demonstrates that they can offer significant delay and energy-per-bit improvements in high-performance circuits at the end of the roadmap. Performances of various design scenarios that comprise one or a few parallel individual SWNT interconnects are compared against the performance of the conventional Cu/low- k interconnect technology at future technology nodes using delay, energy per bit, and energy-delay product as metrics.

Technology/Circuit/System Co-Optimization and Benchmarking for Multilayer Graphene Interconnects at Sub-10-nm Technology Node

Based on realistic circuit- and system-level simulations, graphene interconnects are analyzed in terms of multiple material properties, such as the mean free path (MFP), the contact resistance, and the edge roughness. The benchmarking results indicate that the advantage of using graphene interconnects occurs only under certain circumstances. The device-level parameters, including the supply and threshold voltages, and the circuit-level parameters, including the wire length and width, have large impacts on both the delay and energy-delay product (EDP). At the circuit level, one representative circuit, a 32-bit adder, is investigated, where up to 40% and 70% improvements in delay and EDP are observed. At the system-level analysis, an ARM Cortex-M0 processor is synthesized, and placement and routing are performed. After replacing copper interconnects with multilayer graphene interconnects, up to 15% and 22% performance improvements in clock frequency and EDP have been observed. It is also demonstrated that the benefits of using graphene for the ARM core processor are strongly dependent on the quality of the graphene, such as the MFP and the edge roughness.

Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices

The trade-offs between the technology parameters of various interconnect technologies are investigated on the basis of their impacts on the circuit performances of emerging post-CMOS devices. In this paper, carbon nanotube field-effect transistor (CNFET), nanowire-based gate-all-around (GAA) tunneling field-effect transistor (TFET), FinFET and sub-threshold CMOS circuits are studied. Each of these devices are paired with the conventional Cu/low-k interconnect, single-wall carbon nanotube (SWNT) interconnect manufactured in horizontal bundles or in a single layer, and multi-layer graphene nanoribbon (GNR) interconnect. The relative performances of all these interconnect technologies with each type of device are evaluated. The interconnect technology option that gives the best performance in terms of circuit delay, energy-per-bit and energy-delay product (EDP) is reported for each of the device technologies.

BEOL Scaling Limits and Next Generation Technology Prospects

This paper presents the major limitations to the interconnect technology scaling at future technology generations and demonstrates both evolutionary and radical potential solutions to the BEOL scaling problem. To address the local interconnect challenges, a novel hybrid Al-Cu interconnect technology is introduced. Performances of carbon-based interconnects are evaluated as a more radical solution. The impact of interconnects and the optimal interconnect options are investigated for emerging next generation devices. Interconnects for new state variables, namely spintronic interconnects, are studied and their potential performances in an all-spin logic system are evaluated.

Adapting Interconnect Technology to Multigate Transistors for Optimum Performance

Beyond the 22-nm technology node, interconnect parasitics are increasingly contributing to the degradation of circuit performance. Thus, the focus is on optimizing interconnect parasitics in order to achieve optimum performance. The increased total device capacitance and the reduced device resistance of multigate transistors amplify the importance of wire resistance in circuit delay. In this paper, the impact of interconnect resistance on the circuit performance is weighed against interconnect capacitance, and less aggressive wire width and thickness scaling are proposed. This analysis is carried out based on the results from fully timing-closed, GDSII-level layout of circuit blocks, for the 11- and 7-nm technology nodes. The sensitivity of circuit power dissipation and signal noise to interconnect dimensions is assessed in detail. This approach compromises wire capacitance and gradually renders it important in circuit delay. The circuit performance enhancement by air-gap (AG) interconnect technology is studied with the traditional BEOL scaling versus the proposed wire sizing. It is found that using the latter wire sizing approach with air-gap interconnects is more beneficial to circuit performance.

Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts

In this paper, we investigate the impact of local interconnect size effects on the performance of integrated circuits (ICs) based on timing-closed GDSII-level layouts of circuit blocks with detailed routing. For this purpose, we create multiple standard cell and interconnect libraries for 45-, 22-, 11- and 7-nm technology nodes considering scaling trends projected by the International Technology Roadmap for Semiconductors (ITRS) and assuming various sets of size effect parameters. We make comparisons between the performances of circuit designs that are implemented using these libraries.

Evaluating Chip-Level Impact of Cu/Low-

Dimensional scaling of interconnects at future technology generations presents major limitations to the improvement of the performances of integrated circuits. In this paper, we investigate the impact of highly scaled Cu/low-κ interconnects on the speed and power dissipation of multiple circuit blocks based on timing-closed full-chip Graphic Database System II (GDSII)-level layouts with detailed routing. First, we build multiple standard cell libraries for 45-, 22-, 11-, and 7-nm technology nodes and model their timing/power characteristics. Next, we pair these standard cell libraries with various interconnect files and build GDSII-level layouts for multiple benchmark circuits to study the sensitivity of the circuit performance and power dissipation to multiple interconnect technology parameters such as resistivity, barrier/liner thickness, and via resistance. We investigate the implications of slowing down interconnect dimensional scaling below 11-nm technology node.

\kappa

The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device- and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single- and multi-core processors. Several performance metrics have been analyzed, which shows that optimal numbers of cores, power density and die size area exist for maximizing various design targets.

Performance Degradation on Circuit Performance at Future Technology Nodes

This paper investigates the performances of conventional Cu/low- k multilevel interconnect networks (MINs) for FinFETs at the 20-, 16-, 14-, 10-, and 7-nm technology nodes corresponding to the even years between 2012 and 2020, respectively. This paper captures the impacts of interconnect variables, such as size effect parameters, barrier/liner bilayer thickness, and aspect ratio on the design and performance of the MIN of a logic core. The number of metal levels for a high-performance chip increases by as large as 34% due to size effects, and this value can go up to 76% considering issues in barrier/liner thickness scaling at the 7-nm technology node. At this node, increasing the aspect ratio of interconnects from two to three can improve wire delay and save two metal levels at the cost of 35% more power dissipation. A ±20% wire-width variation induces wire delay variations of -20% and 44% at minimum-width wires. Designing the MIN considering this variation increases the required wire area by 4% in the worst case.

System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs

The impact of size effects such as surface and grain boundary scatterings and line edge roughness (LER) on the design of a multi-level interconnection network, and potential power saving offered by individual single-wall nanotube (SWNT) and mono-layer graphene interconnects are investigated and quantified for high-performance and low-cost designs implemented at future technology nodes. It is shown that size effects increase the number of metal levels for a high performance chip by as large as 22.81% and 41.35% at the 21nm and 7.5nm technology nodes, respectively. It has also been demonstrated that individual metallic SWNT and mono-layer graphene interconnects may be used to reduce the interconnect power dissipation in both high-performance and low-cost designs at the end of the roadmap. This is in contrast to previous publications which all indicated that bundles of densely packed SWNTs are needed for interconnect applications.