Rouhollah Mousavi Iraei

Circuit Simulation of Magnetization Dynamics and Spin Transport

In this paper, compact circuit models for spintronic devices have been developed by manipulating the underlying physical equations. We have simulated, via circuit simulation: 1) the magnetization dynamics governed by the Landau-Lifshitz-Gilbert (LLG) equation and 2) the spin transport physics governed by the spin drift-diffusion equation. The models have been validated using numerical and analytical solutions of the LLG equation and the spin drift-diffusion equations, respectively. Simulations of an all-spin logic device demonstrate the applications of the developed models in device and circuit simulation.

Design and Analysis of Copper and Aluminum Interconnects for All-Spin Logic

In this paper, a conventional spin-valve configuration combined with spin-torque-driven switching is used as an energy efficient interconnect structure for all-spin logic. Both Cu and Al interconnect materials are analyzed based on physical models for spin injection, spin transport, and magnetization dynamics. The results indicate proposed metallic interconnects dissipate less energy as compared with all-spin logic interconnects based on the nonlocal spin-valve configuration. Compared with a similar spin interconnect with an Si channel, the spin currents and injection efficiencies are predicted to be higher when a metal like Cu or Al is used due to no Schottky barrier at the interface. Because of the longer spin relaxation length (SRL) in Al as compared with Cu, the delay and energy dissipation are lower when Al is used especially at longer lengths where signal loss becomes important. While metallic spin interconnects are faster and more energy efficient in short lengths because of their smaller resistances and higher spin injection efficiencies, they are outperformed by spin interconnects with Si channels at long lengths because the SRLs in Si can be as long as many micrometers, whereas in metals they are limited to a few hundred nanometers.

BEOL Scaling Limits and Next Generation Technology Prospects

This paper presents the major limitations to the interconnect technology scaling at future technology generations and demonstrates both evolutionary and radical potential solutions to the BEOL scaling problem. To address the local interconnect challenges, a novel hybrid Al-Cu interconnect technology is introduced. Performances of carbon-based interconnects are evaluated as a more radical solution. The impact of interconnects and the optimal interconnect options are investigated for emerging next generation devices. Interconnects for new state variables, namely spintronic interconnects, are studied and their potential performances in an all-spin logic system are evaluated.

Impact of dimensional scaling and size effects on beyond CMOS All-Spin Logic interconnects

The energy-per-bit and delay of All-Spin Logic (ASL) interconnects have been modeled. Both Al and Cu interconnect channels have been considered and the impact of size effects and dimensional scaling on their potential performance has been quantified. It is predicted that size effects will affect ASL interconnects more severely than electrical interconnects.

Impact of spintronics transducers on the performance of spin wave logic circuit

We propose a comprehensive scheme for building spintronics transducers for back and forth signal conversion between spin and charge domains in addition to the associated CMOS peripheral circuitry for spin wave device (SWD) circuits. We perform systematic analysis of the impact of the transducers on the performance of SWD in terms of energy and area overhead. Performance evaluation of SWD compared with 7nm FinFET CMOS technology at the circuit level, yields a 3× smaller area and an order of magnitude lower energy-delay product (EDP) for large complex circuits with low overhead. Overall, SWD outperforms CMOS with increasing ratio of (logic size/overhead).

Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition

We present a new circuit for non-Boolean recognition of binary images. Employing all-spin logic (ASL) devices, logic comparators and non-Boolean decision blocks for compact and efficient computation are designed. By manipulation of fan-in number in different stages of the circuit, the structure can be extended for larger training sets or larger images. Operating based on the main similarity idea, the system is capable of constructing a mean image and compare it with a separate input image within a short decision time. Taking advantage of the nonvolatility of ASL devices, the proposed circuit is capable of hybrid memory/logic operation. Compared with the existing CMOS pattern recognition circuits, this paper achieves a smaller footprint, lower power consumption, faster decision time, and a lower operational voltage.

A proposal for a magnetostriction-assisted all-spin logic device

As scaling CMOS devices is approaching its fundamental limits, a new direction of research has emerged to study beyond-CMOS spintronic devices that use electronic spin as their state variable, offering new and enhanced functionalities. Due to low operating voltage, non-volatility, and efficient implementation of majority gate, a novel spin-based device, all-spin logic (ASL), has been widely studied for applications including interconnects [1], pattern recognition systems [2], and Boolean gates [3]. However, ASL relies on a non-local spin valve (NLSV) structure with the connection to ground being close to the input magnet to ensure non-reciprocity. Thus, a large fraction of injected spins is shunted to ground without ever reaching the output magnet. In addition, supply clocking is envisioned to reduce energy dissipation [3]. Even then, a 32-bit addition by ASL compared to that by CMOS, requires 5 orders of magnitude more energy. In this paper, we propose a novel device that uses voltage-controlled strain-mediated magnetization switching [4] and spin transfer torque (STT) to perform the first and second 900 of switching, respectively. The STT is created in a conventional spin valve instead of the NLSV structure used in ASL. Hence, the wasteful shunt path to ground is eliminated. Non-reciprocity is ensured through a clocking scheme in which the input and output magnets are oriented along the stable easy axis and the meta-stable saddle point of energy profile, respectively. It has been shown that the deterministic switching of a magnet from a saddle point is more efficient in terms of delay and energy and affected less by thermal noise [5], [6]. The device can be cascaded in a domino logic scheme, Fig. 1 a, by performing the first 900 switching for all cascaded logic gates simultaneously; therefore, the overall delay of a more complicated circuit like a 32-bit adder significantly improves.

Hybrid piezoelectric-magnetic neurons: a proposal for energy-efficient machine learning

This paper proposes a spintronic neuron structure composed of a heterostructure of magnets and a piezoelectric with a magnetic tunnel junction (MTJ). The operation of the device is simulated using SPICE models. Simulation results illustrate that the energy dissipation of the proposed neuron compared to that of other spintronic neurons exhibits 70% improvement. Compared to CMOS neurons, the proposed neuron occupies a smaller footprint area and operates using less energy. Owing to its versatility and low-energy operation, the proposed neuron is a promising candidate to be adopted in artificial neural network (ANN) systems.