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Featured researches published by Cheoljon Jang.


advanced information networking and applications | 2012

IEC 61850 Standard Based MMS Communication Stack Design Using OOP

Jongjoo Park; Eunkyu In; Sangwoo Ahn; Cheoljon Jang; Jong-Wha Chong

This paper deals with the MMS communication stack library based on IEC 61850 standard. IEC 61850 standard is communication protocol of substation automation for converting conventional copper-wired type to Ethernet based open architecture in digital method. With IEC 61850 standard, interoperability can be maximized. With IEC 61850, optimal use and prediction of troubles are done through real-time surveillance by substation system. Starting from European market, substation automation systems (Sass) based on IEC61850 are spreading trend. Trying to stay with the trend, communication stack library is needed. IEC 61850 standard consists of object, we adopt the strategy of using object-oriented programming (OOP) based on C++ language. Therefore we can take advantages of maintenance, management, alteration and reuse. For improving power of OOP method, we adopt design pattern, especially singleton pattern. With these two strategies, this paper layers the library into a dozen or more layer to provide developers ease of use. We simulate this library by making Microsoft Windows programs.


Iet Computers and Digital Techniques | 2013

Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits

Cheoljon Jang; Jaehwan Kim; Byung-Gyu Ahn; Jong-Wha Chong

Three-dimensional-integrated circuits (3D-ICs) bring new issues for power delivery network design because of larger current density and more complicated power delivery paths compared to 2D-IC. The power delivery network consists of power bumps, through-silicon-vias (TSVs), and power wires. IR-drop at each node varies with the number and position of power bumps and TSVs. These three power resources affect IR-drop of 3D-ICs. In this study, the authors propose power delivery network design methodology to optimise power resources wherease IR-drop constraint is satisfied. The simulation results show that the proposed method minimises the number of power bumps and TSVs compared to the conventional method.


international symposium on consumer electronics | 2014

Timing driven global router with a pin partition method for 3D stacked integrated circuits

Jiho Song; Cheoljon Jang; Kyungin Cho; Seungryeol Go; Jong-Wha Chong

Three-dimensional (3D) integration technology packs together multiple active device dies, achieving a higher level of integration within a given footprint. However, due to an increase in the design volume and complexity, routing has become a challenging problem in 3D IC designs. In this paper, we propose a timing driven routing algorithm for 3D IC with a load balancing method that distributes the capacitance of the interconnections including TSV. In the load balancing step, the sink pins are partitioned to balance the loads within the routing tree. The routing trees are then created by merging the sub-trees that are generated with the balanced group.


international symposium on consumer electronics | 2014

Thermal aware clock tree optimization with balanced clock skew in 3D ICs

Kyungin Cho; Cheoljon Jang; Jiho Song; Sangdeok Kim; Jong-Wha Chong

Thermal issues are a primary concern in the three-dimensional integrated circuit (3D IC) design. This paper addresses a clock tree synthesis problem under thermal variation for 3D IC designs. Our major contributions are the reduced and balanced skew with minimum wirelength under both nonuniform and uniform thermal conditions. Our proposed clock tree synthesis algorithms search the routing path to find the clock merging point at each level of the clock tree. Experimental results show that our methods significantly reduce and balance clock skew values with the minimum wirelength overhead.


networked embedded systems for enterprise applications | 2011

Design of one chip communication stack processor and MMS communication stack library based on IEC 61850

Eunkyu In; Jongju Park; Sangwoo Ahn; Cheoljon Jang; Jong-Wha Chong

This paper deals with implementation of a MMS Communication stack library used in the processor and an IEC 61850 one chip communication stack processor of an IED used in a SAS server and a client. According to the definitions of IEC 61850 standards, communication services of SAS are divided mainly into three steps: initialization, processing and communication step. The three steps above defined in IEC 61850 standards are designed by using object-oriented programing language; C++. By using the IEC 61850 one chip communication stack processor, the processor makes it easy to manage and repair an IED, and supports compatibility between IEDs of different manufacturers. By using the IEC 61850 MMS communication stack library, not only users development hours are reduced but also it contributes to the automation of substation.


Etri Journal | 2014

Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs

Cheoljon Jang; Jong-Wha Chong


Etri Journal | 2014

Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated Circuits

Kyungin Cho; Cheoljon Jang; Jong-Wha Chong


Archive | 2014

METHOD OF DESIGNING POWER SUPPLY NETWORK

Myung-Soo Jang; Jae-Rim Lee; Jong-Wha Chong; Jaehwan Kim; Byung-Gyu Ahn; Cheoljon Jang


Archive | 2014

METHOD OF DESIGNING ARRANGEMENT OF TSV IN STACKED SEMICONDUCTOR DEVICE AND DESIGNING SYSTEM FOR ARRANGEMENT OF TSV IN STACKED SEMICONDUCTOR DEVICE

Myung-Soo Jang; Jae-Rim Lee; Jong-Wha Chong; Minbeom Kim; Wen Rui Li; Cheoljon Jang


Iet Computers and Digital Techniques | 2014

Power-aware floorplanning-based power throughsilicon- via technology and bump minimisation for three-dimensional power delivery network

Cheoljon Jang; Jaehwan Kim; Jong-Wha Chong

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