Byung-Gyu Ahn

Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs

Higher integrated density in 3D ICs also brings the difficulties of routing, which can cause the routing failure or re-design from beginning. Hence, precise congestion estimation at the early physical design stage such as floorplan is beneficial to reduce the total design time cost. In this paper, an effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage. This method uses synthesized virtual signal nets, power/ground network and clock network to achieve the estimation. During the synthesis, the TSV location is also under consideration. The experiments indicate that our proposed method had small difference with the estimation result got at the post-placement stage. Furthermore, the comparison of congestion maps obtained with our method and global router demonstrates that our estimation method is able to predict the congestion hot spots accurately.

Thermal aware timing budget for buffer insertion in early stage of physical design

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology which contains the estimated thermal distribution on a chip in the early stage of physical design by modeled the RC delay considering temperature and buffer insertion planning using by the proposed delay model are presented. Simulation results showed the reduction of the worst delay after buffer insertion up to 30% in contrast to the buffer insertion without considering temperature.

Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits

Three-dimensional-integrated circuits (3D-ICs) bring new issues for power delivery network design because of larger current density and more complicated power delivery paths compared to 2D-IC. The power delivery network consists of power bumps, through-silicon-vias (TSVs), and power wires. IR-drop at each node varies with the number and position of power bumps and TSVs. These three power resources affect IR-drop of 3D-ICs. In this study, the authors propose power delivery network design methodology to optimise power resources wherease IR-drop constraint is satisfied. The simulation results show that the proposed method minimises the number of power bumps and TSVs compared to the conventional method.

A novel methodology for power delivery network optimization in 3-D ICs using through-silicon-via technology

Three-dimensional integrated circuits (3-D IC) are available through the die-stacking and through-silicon-via (TSV) technologies. The 3-D IC using the TSV brings the performance improvement through the minimization of wire length and footprint area. However, the 3-D ICs have many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2-D ICs. The power delivery network in 3-D IC with flip chip package is largely composed of power/ground (P/G) bumps and P/G TSVs. Because the number of P/G bumps is limited and the size of P/G TSV is larger than that of standard cell, it is important to optimize the P/G bumps and P/G TSVs together while satisfying the IR-drop constraint. In this paper, we investigated an effect of the number of power bumps and power TSVs on the IR-drop in 3-D IC floorplan level and proposed the methodology that reduces the number of power bumps by 88.25% on average while the number of power TSVs and maximum IR-drop are comparable to the previous methodology.

Thermal Aware Buffer Insertion in the Early Stage of Physical Designs

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.

Timing driven force-directed floorplanning with incremental static timing analyzer

As nano-scale technology is widely adopted, minimizing the interconnection delay has become one of the most critical issues in designing high performance systems. To achieve fast timing closure, it is very important to estimate the interconnection delay accurately at an early design stage. In this paper, we propose a novel timing driven force-directed floorplanning technique using an efficient incremental static timing analyzer. Our proposed floorplan framework contains a fast and accurate interconnection delay estimator which is very important to obtain an excellent floorplan. The proposed timing methodology has been implemented as a part of a commercial floorplanning tool called Pillar-DP from Entasys Design Inc. We carried out experiments on several benchmarks to show the effectiveness of our approach. The experiment results show that our tool is valuable in generating a near optimal floorplan within a reasonable amount of time.