Cheryl Stout

10 Gb/s silicon bipolar 8:1 multiplexer and 1:8 demultiplexer

High-speed multiplexer and demultiplexer circuits are key components in high-speed optical communication systems such as SONET. As optical communication link speeds increase, faster electronic interface circuitry is required. The use of multiplexer circuits allows most of the electronic circuitry to operate on parallel data at a lower speed, reducing the speed requirements of much of the system. A retimed 8:1 multiplexer and a 1:8 demultiplexer which operate at 10 Gb/s are described. These circuits were fabricated in high-speed silicon bipolar process. Design optimization techniques were used to achieve maximum performance. The retimed multiplexer and the demultiplexer dissipate 3.8 and 4.3 W, respectively. >

A 2.488 Gb/s Si-bipolar clock and data recovery IC with robust loss of signal detection

SONET 2.488Gb/s transmission and switching systems, network backbones, and video transmission are among the many application areas benefiting from inexpensive and robust clock and data recovery circuits (CDR). Previous commercial solutions have required multiple chips and GaAs processes to perform this function. This 25GHz f/sub T/ Si-bipolar chip operates from 2 to 3Gb/s over worst-case process, temperature and voltage variations, dissipating 1.77W from 5V/spl plusmn/10% supply, requiring a single off-chip filter capacitor. For network monitoring, a loss-of-signal (LOS) detector operates on phase-error events, with a trigger threshold programmable between 10/sup -4/ and 10/sup -6/ BER.

A 2-chip 1.5 Gb/s bus-oriented serial link interface

The authors report a monolithic transmitter and receiver chip pair which implements a full-duplex virtual ribbon cable interface. For short-distance applications, on-chip equalizer is provided to allow use of coaxial cables rather than a more costly fiber link. The chips require no external frequency-determining elements or user adjustments and operate over a range of 600 to 1500 MHz using an on-chip VCO (voltage-controlled oscillator). Only one in-package capacitor per chip is required. A state-machine controller (SMC) is also implemented on the RX chip to transparently handle a start-up handshake protocol. This is the highest-speed-link-interface chipset reported to date at this level of functionality and integration.<<ETX>>

A 1.5 GBaud/sec Serial Link Monolithic Chip Set

A 1.5 GBaud/s serial data link comprised of a 2-chip set capable of transporting up to 21 parallel bits was successfully fabricated using a 25 GHz peak ft silicon bipolar process. This link features a new encoding scheme which allows DC balance in the serial stream, as well as an internally generated clock which phase locks to the users clock at the transmitter, and full clock recovery and data retiming at the receiver. In addition, a controller integrated with the link handles handshaking at start up for full duplex operation.

A general-purpose link interface chipset for gigabit rate data communication

A chipset has been developed for transmitting parallel data over serial links. The chipset, consisting of a transmitter interface chip (TIC) and a receiver interface chip (RIC), can support serial transmission up to 1.4 Gbaud. Data encoding is based on a scheme published earlier, but has been improved to provide more flexibility and better efficiency. The chipset requires no external components for its operation other than a few capacitors, which are built into its custom package.<<ETX>>