Chu-Sun Yen

A 1.5 Gb/s link interface chipset for computer data transmission

The authors designed a set of four ICs to provide encoding, multiplexing, clock extraction/demultiplexing, and decoding for gigabit-rate serial data transmission. These chips form a high bandwidth data link for point-to-point communication. A new line code is implemented that provides DC balance, efficient encoding, framing, and simple clock extraction. Embedded in the code is a fixed transition used by the phase/frequency locked loop (PLL) for simple clock extraction and frame synchronization. Unlike other links, this PLL requires no trimming for data retiming, either in production or later. An on-chip voltage-controlled oscillator (VCO) with a tuning range of 1.1-1.6 GHz is available for use with the PLL. With this chip set the authors demonstrated a transmission rate of 16 bits in parallel at 75 MHz or, with encoding overhead, a serial rate of 1.5 Gb/s. >

A 2.488 Gb/s Si-bipolar clock and data recovery IC with robust loss of signal detection

SONET 2.488Gb/s transmission and switching systems, network backbones, and video transmission are among the many application areas benefiting from inexpensive and robust clock and data recovery circuits (CDR). Previous commercial solutions have required multiple chips and GaAs processes to perform this function. This 25GHz f/sub T/ Si-bipolar chip operates from 2 to 3Gb/s over worst-case process, temperature and voltage variations, dissipating 1.77W from 5V/spl plusmn/10% supply, requiring a single off-chip filter capacitor. For network monitoring, a loss-of-signal (LOS) detector operates on phase-error events, with a trigger threshold programmable between 10/sup -4/ and 10/sup -6/ BER.

1-Gword/s pseudorandom word generator

An integrated circuit that generates 16-bit pseudorandom words at up to 1 Gword/s is presented. The concept of a pseudorandom word sequence is introduced. The pseudorandom words shown have excellent properties for testing serial or parallel components and data links. If serialized, the words would form a pseudorandom bit sequence with a potential maximum serial bit rate of 16 Gb/s. The circuit was implemented in an advanced silicon bipolar process with an f/sub T/ of 10 GHz. The chip includes 16 output drivers, with adjustable amplitude and offset, capable of driving 25- Omega loads with 0.8-V swings and 400-ps rise times. Total chip dissipation is under 4 W on a 2-mm*2-mm die. >

A 2-chip 1.5 Gb/s bus-oriented serial link interface

The authors report a monolithic transmitter and receiver chip pair which implements a full-duplex virtual ribbon cable interface. For short-distance applications, on-chip equalizer is provided to allow use of coaxial cables rather than a more costly fiber link. The chips require no external frequency-determining elements or user adjustments and operate over a range of 600 to 1500 MHz using an on-chip VCO (voltage-controlled oscillator). Only one in-package capacitor per chip is required. A state-machine controller (SMC) is also implemented on the RX chip to transparently handle a start-up handshake protocol. This is the highest-speed-link-interface chipset reported to date at this level of functionality and integration.<<ETX>>

A chipset for gigabit rate data communication (using optical fibres)

A gigabit-rate data link consisting of four custom silicon bipolar chips for transmitting parallel data between elements of a distributed computer system is discussed. A transmission rate of 16 bits in parallel at 50 MHz or with encoding overhead, a serial rate of 1 Gb/s is demonstrated. The link utilizes an encoding scheme that is bandwidth efficient. Unlike other links, the phase/frequency-locked loop also provides frame synchronization and requires no trimming for data retiming, either in production or later.<<ETX>>

A general-purpose link interface chipset for gigabit rate data communication

A chipset has been developed for transmitting parallel data over serial links. The chipset, consisting of a transmitter interface chip (TIC) and a receiver interface chip (RIC), can support serial transmission up to 1.4 Gbaud. Data encoding is based on a scheme published earlier, but has been improved to provide more flexibility and better efficiency. The chipset requires no external components for its operation other than a few capacitors, which are built into its custom package.<<ETX>>