Chetan Gupta

Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model

In this paper, an analytical model of threshold voltage for bulk MOSFET is developed. The model is derived from the physical charge-based core of BSIM6 MOSFET model, taking into account short channel effects, and is intended to be used in commercial SPICE simulators for operating point information. The model is validated with measurement data from IBM 90-nm technology node using various popular threshold voltage extraction techniques, and good agreement is obtained.

Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs

In this paper we present a model to capture the effect of the body-bias on the overlap capacitances. The main hurdle while introducing body-bias dependence in gate-source and gate-drain overlap capacitances is maintaining reciprocity for all capacitances. We propose a subcircuit approach to help maintain reciprocity while including body-bias dependence in overlap charges. The approach is generic, and works for any device. The model has been implemented in BSIM6 industry standard model and has been validated with TCAD simulations as well as experimental measurements.

The Market's Law of Privacy: Case Studies in Privacy and Security Adoption

It might be possible for individual actors in a marketplace to drive the adoption of particular privacy and security standards. Using HTTPS, two-factor authentication, and end-to-end encryption as case studies, the author tries to ascertain which factors are responsible for successful diffusion that improves the privacy of a large number of users.

Analysis and modeling of capacitances in halo-implanted MOSFETs

In this paper, we report the anomalous behavior of capacitances in halo channel MOSFET for the linear and saturation regions. Unlike MOSFETs these devices have different threshold voltage (VTH) for the DC and CV operations, and therefore cannot be modeled by conventional methods. We have investigated various cases of doping non-uniformity: Source side halo (SH), Drain side halo (DH), both side halos (Halo) and uniformly doped (UD) transistors using TCAD simulations under various bias conditions. A computationally efficient SPICE model is used to model these trends which shows excellent matching with the measured and TCAD data.

Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model

In this paper, we present the modeling of zero-threshold voltage (V TH) bulk MOSFET, also called native devices, using enhanced BSIM6 model. Devices under study show abnormally high leakage current in weak inversion, leading to degraded subthreshold slope. The reasons for such abnormal behavior are identified using technology computer-aided design (TCAD) simulations. Since the zero-V TH transistors have quite low doping, the depletion layer from drain may extend upto the source (at some non-zero value of V DS) which leads to punch-through phenomenon. This source–drain leakage current adds with the main channel current, causing the unexpected current characteristics in these devices. TCAD simulations show that, as we increase the channel length (L eff) and channel doping (N SUB), the source–drain leakage due to punch-through decreases. We propose a model to capture the source–drain leakage in these devices. The model incorporates gate, drain, body biases and channel length as well as channel doping dependency too. The proposed model is validated with the measured data of production level device over various conditions of biases and channel lengths.

Modeling of high voltage LDMOSFET using industry standard BSIM6 MOS model

In this paper we have shown the modeling of Lateral Double-Diffused MOS (LDMOS) transistor. A LDMOS structure can be divided into two parts, intrinsic channel and extended drift region. The intinsic channel region is modeled by industry standard BSIM6 model and extended drift region has been modeled by the modified CMC standard model of R3. The R3 model of non-linear resistor, which includes physical effects like velocity-saturation, self-heating etc. has been modified to include gate bias dependency. The new model has been validated with technology computer-aided design (TCAD) simulations and measured data from ON Semiconductor. The model (which is the combination of BSIM6 and R3 models) shows excellent agreement with the TCAD simulations and measured data.