Chi-I Lang

High-Productivity Combinatorial PVD and ALD Workflows for Semiconductor Logic & Memory Applications

With materials innovation driving recent logic and memory scaling in the semiconductor industry, High-Productivity Combinatorial™ (HPC) technology can be a powerful tool for finding optimum materials solutions in a cost-effective and efficient manner. This paper will review unique HPC wet processing, physical vapor deposition (PVD), and atomic layer deposition (ALD) capabilities that were developed, enabling site-isolated testing of multiple conditions on a single 300mm wafer. These capabilities were utilized for exploration of new chalcogenide alloys for phase change memory, and for metal gate and high-K dielectric development for high-performance logic. Using an HPC PVD chamber, a workflow was developed in which up to 40 different precisely controlled GeSbTe alloy compositions can be deposited in discrete site-isolated areas on a single 300mm wafer and tested for electrical & material properties, using a custom in-situ high-throughput sheet-resistance measurement setup, to get very accurate measurements of the amorphous – crystalline transition temperature. We will review how resistivity as a function of temperature, crystallization temperature, final and intermediate (if any) crystalline phases were mapped for a section of the GeSbTe phase diagram, using only a few wafers. Another area where HPC can be very valuable is for finding optimum materials for high-k dielectrics and metal gates for high-performance logic transistors. Assessing the effective work-function (EWF) for a given high-k dielectric metal-gate stack for PFET and NFET transistors is a critical step for selecting the right materials before further integration. One way to obtain EWF is by using a terraced oxide wafer with different SiO2 thickness bands underneath the high-k dielectric. We report a HPC workflow using our wet, ALD & PVD capabilities, to quickly assess EWF for multiple different high-k dielectrics and metal gate stacks. This workflow starts with a HPC wet etch of thermal silicon oxide, creating different oxide thicknesses 1–10nm in select areas of the same substrate. This is followed by atomic layer deposition of a high-k dielectric film such as HfO2. Next, a metal e.g., TaN is deposited through a physical mask or patterned post-deposition to complete the formation of MOS capacitors. The final step is C-V measurements and C-V modeling to extract Vfb, high-k dielectric constant, EOT, and EWF from Vfb vs EOT plot. This workflow was used to extract EWF for a TaN metal gate with an ALD HfO2 high-k dielectric using a metal-organic precursor. We will discuss how EWF for this system was affected by annealing post-dielectric deposition & post-metallization, different annealing temperatures & ambients, Hf pre-cursors and interfacial cap layers e.g., La2O3 & Al2O3. Finally, we will also discuss more advanced versions of this workflow where the ALD high-k dielectric and PVD metal gate is also varied on the same wafer using HPC versions of ALD & PVD chambers.