Philip A. Kraus

Model to predict gate tunneling current of plasma oxynitrides

Two key parameters for silicon MOSFET scaling, equivalent oxide thickness (EOT) and gate leakage current density (J/sub g/) are measured and modeled for silicon oxynitride (Si-O-N) gate dielectrics formed by plasma nitridation of SiO/sub 2/. It is found that n-MOSFET inversion J/sub g/ is larger than p-MOSFET inversion J/sub g/ when the gate dielectric consists of less than 27% nitrogen atoms, indicating substrate injection of electrons is dominant for this range of plasma nitrided Si-O-N. To examine the intrinsic scaling of Si-O-N, we model EOT and n-MOSFET J/sub g/ for sub-2-nm physically thick gate dielectrics as a function of film physical thickness and nitrogen content. The model has four free fitting parameters and unlike existing models does not assume a priori the values of the oxide and nitride dielectric constant, barrier height, or effective mass. It indicates that at a given EOT, leakage current of n-MOSFETs with Si-O-N gate dielectrics reaches a minimum at a specific nitrogen content. Through the use of this model, we find that plasma nitrided Si-O-N can meet the 65-nm International Technology Roadmap for Semiconductors specifications for J/sub g/, and we estimate the nitrogen concentration required for each node and application.

Physical models for predicting plasma nitrided Si-O-N gate dielectric properties from physical metrology

Using simple physical models, specific relationships between parameters measured by X-ray photoelectron spectroscopy (XPS) and those measured on MOS transistors are described for silicon oxynitride gate dielectrics prepared by plasma nitridation. Correlations are established between the equivalent oxide thickness (EOT) and gate leakage current and the nitrogen anneal dose and physical thickness as measured by XPS. These correlations, from devices in the 10 to 13 /spl Aring/ EOT range, allow accurate estimates of electrical thickness and leakage without device fabrication, enabling both development and process monitoring for sub-130-nm node gate dielectrics.

The evaluation of performance parameters of MOSFETs with alternative gate dielectrics

This brief discusses a benchmarking methodology for the evaluation of performance parameters (g/sub mmax/ and I/sub dsat/) of MOSFETs with alternative gate dielectrics. It is shown that assuming ideal scaling for either or with electrical oxide thickness (g/sub mmax/ or I/sub dsat/ /spl prop/ T/sub oxinv//sup -/spl alpha// with /spl alpha/ = 1) instead of using experimental scaling trends for a baseline dielectric results in unrealistically pessimistic conclusions about the performance of alternative gate dielectrics. Factors In addition to mobility reduction which can contribute to sub-ideal scaling (/spl alpha/ < 1) for any dielectric are discussed. This bench marking methodology for performance evaluation is demonstrated for oxynitride gate dielectric films with equivalent oxide thickness (EOT) approaching 11 /spl Aring/.

Observation of nitrogen-enhanced doping deactivation at the polysilicon-oxynitride interface of pMOSFETs with 12-/spl Aring/ gate dielectrics

This letter reports the observation of a process integration issue that arises when large doses of nitrogen (>1/spl times/10/sup 15/ cm/sup -2/) are incorporated in oxynitride gate dielectric films targeting equivalent oxide thickness of 11-13 /spl Aring/. It is shown that capacitance-extracted active doping density at the polysilicon/oxynitride (poly/SiON) interface of boron-doped p/sup +/-polysilicon gated pMOSFETs decreases with increasing nitrogen dose of the oxynitride film as measured by X-ray photoelectron spectroscopy. A physical mechanism is proposed to explain experimental observations.

Trends in gate stack engineering

MOSFET scaling requires an increase in the dielectric capacitance and hence a decrease in the dielectric electrical thickness. In this paper, we review the scaling trends for the gate dielectric and the gate electrode as the industry faces the challenges of introducing new materials into production.

Interface Trap Characterization of Alternate Gate Dielectrics With Elastic Gate MOS Metrology

The replacement of SiO2 by alternative gate dielectrics, such as high‐nitrogen content oxynitrides or high‐κ metallic oxides (e.g. HfO2), in advanced CMOS technology requires an investigation of the interface quality between the dielectric and the Si substrate. An accurate, precise and convenient metrology for the characterization of the interface trap density (Dit) would be useful to evaluate the hardware, processes and integration schemes for the formation of alternative gate dielectrics. We report the extraction of mid‐gap Dit by implementing a well‐known conductance method from small‐signal measurements of MOS impedance for plasma‐nitrided oxynitrides. Here the MOS system is not formed from the fabrication of a device, but through the use of an elastic metal gate (EM‐gate) metrology system where measurements are made on unpatterned films. The technique allows rapid evaluation of the interface quality for new gate dielectric materials and processes.

Electron neutral collision frequency measurement with the hairpin resonator probe

Electron neutral collision frequency is measured using both grounded and floating hairpin resonator probes in a 27 MHz parallel plate capacitively coupled plasma. Operating conditions are 0.1–2 Torr (13.3–267 Pa) in Ar, He, and Ar–He gas mixtures. The method treats the hairpin probe as a two wire transmission line immersed in a dielectric medium. Measurements are obtained using a pressure and sheath correction process by sweeping over assumed collision frequencies in order to obtain the measured collision frequency. Results are compared to hybrid plasma equipment module simulations and show good agreement.

Silicon interface trap characterization with elastic metal gate metrology

The replacement of SiO2 by oxynitride or high-κ materials as the gate dielectric in advanced Si complementary metal–oxide–silicon (CMOS) technology requires an investigation of the interface quality between the dielectric and the Si substrate for any candidate dielectric. An accurate, precise and convenient metrology for the characterization of the interface trap density (Dit) would be useful to evaluate the hardware, processes, and integration schemes for the formation of alternative gate dielectrics. In this article, we report the extraction of Dit near mid-gap by implementing a well-known conductance method from small-signal measurements of MOS impedance for oxynitrides with a range of physical thicknesses and nitrogen content. The MOS system measured in this work is not formed from the fabrication of a device, but through the use of an elastic metal gate metrology system where measurements are made on unpatterned films. The technique allows rapid, precise, and quantitative information on the interface...

Nanoscale materials modification via low-energy reactive plasmas

Materials modification of thin films and nanoparticles through the use of reactive plasmas is discussed. Pulsed radio-frequency nitrogen plasmas have been well characterized through measurement of the ion energy distribution in the plasma. The low-energy nitrogen plasmas are successfully used for nitrogen incorporation into ultrathin MOSFET gate dielectrics, where nitrogen dose control and nitrogen profile control are both critical. The use of low-energy, pulsed radio-frequency reactive plasmas for other applications where composition and morphology need to be controlled at the nanometer scale is considered.