Chiakang Sung

A dual granularity and globally interconnected architecture for a programmable logic device

A novel architecture called FLEX (flexible logic element matrix) has been designed which supports high logic densities up to 24,000 gates, maximizing overall system performance in a user design. This has been accomplished through a dual granularity approach and a global interconnect strategy. The dual granularity and global interconnect approach has succeeded in supporting both short nets and long nets for maximum performance.

A high density embedded array programmable logic architecture

An SRAM based embedded array programmable logic architecture with densities ranging from 10000 to 100000 gates is discussed in this paper. An embedded array is incorporated into this architecture to implement megafunctions like microprocessors, FIFOs and multipliers efficiently. A multidimensional interconnect scheme is featured to achieve flexible routing between logic blocks, the embedded array and I/O pins. The first member of the family is currently available with a gate density of 50000 gates.

A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface

As FPGAs integrate into high-speed systems, performance and signal integrity become more important in I/O design. This paper describes the development of an FPGA design to support 1.6 Gb/s differential source-synchronous standards and 300 MHz external memory interfaces. Speed and performance were achieved using circuits such as differential level-shifters with voltage and temperature compensated current sources, on-chip decoupling capacitors, and floating-well output buffers. Programmable drive strength, output impedance matching, hot-socketing compliance, and 3.3-V voltage tolerance are features of the I/O buffer. In addition, DLLs and programmable phase-offset circuits were used to obtain precise timing control. The chip was manufactured on a 90-nm CMOS process.

Optimizations for a highly cost-efficient programmable logic architecture

Architects of programmable logic devices (PLDs) face several challenges when optimizing a new device family for low manufacturing cost. When given an aggressive die-size goal, functional blocks that seem otherwise insignificant become targets for area reduction. Once low die cost is achieved, it is seen that testing and packaging costs must be considered. Interactions among these three cost contributors pose trade-offs that prevent independent optimization. This paper discusses solutions discovered by the architects optimizing the Altera FLEX 6000 architecture.

A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface

As FPGAs become more integrated into high-speed systems, high performance I/O with excellent signal integrity becomes more important. This paper describes how these challenges were met on an FPGA developed to support 1.6 Gbps differential source-synchronous standards and 300 MHz external memory interfaces. The I/O buffer features programmable drive strength, output impedance matching, hot-socketing compliance, and 3.3v tolerance. High-speed performance was achieved using design techniques of differential level-shifters with voltage and temperature compensated current sources, on-chip decoupling capacitors, and floating-well output buffers. In addition, DLLs and programmable phase offset circuits were used to obtain precise timing control. The chip was manufactured on a 90 nm CMOS process.

A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM

A million gate programmable logic device (PLD) designed for high performance system integration is discussed. The APEX 20K1000E is fabricated on a 0.18 /spl mu/m CMOS process. The chip supports multiple I/O standards with data bandwidth up to 622 Mbps when using the integrated low voltage differential signaling (LVDS) interfaces. Multiple on-chip phase-locked loops (PLL) increase performance and provide clock-frequency synthesis. The embedded content addressable memory (CAM) enhances performance for fast search applications.

A silicon efficient FLEX 6000 programmable logic architecture

An SRAM based PLD architecture ranging from 5000 to 24000 gates has been developed. The primary focus of the architecture is on low cost, high performance, and routability. Breakthroughs in interconnect scheme have been made to achieve flexible routing and high cost efficiency in the interconnect, logic array blocks, and I/O elements. Other architecture features include built-in low skew clock, programmable output slew rate control, PCI compliant I/O, JTAG boundary scan, individual output enable for each I/O pin, and in-circuit configuration. The first member of the family is currently available with 16000 gate density and 125 MHz performance for 16-bit counter application.

Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process

A global interconnect architecture with dual granularity demonstrates considerable migration capability from the original product on 0.8Μ two layer metal process by reducing die size to one third while nearly doubling system frequency when transferred to a 0.5Μ three layer metal process.