Philip Pan

A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface

As FPGAs integrate into high-speed systems, performance and signal integrity become more important in I/O design. This paper describes the development of an FPGA design to support 1.6 Gb/s differential source-synchronous standards and 300 MHz external memory interfaces. Speed and performance were achieved using circuits such as differential level-shifters with voltage and temperature compensated current sources, on-chip decoupling capacitors, and floating-well output buffers. Programmable drive strength, output impedance matching, hot-socketing compliance, and 3.3-V voltage tolerance are features of the I/O buffer. In addition, DLLs and programmable phase-offset circuits were used to obtain precise timing control. The chip was manufactured on a 90-nm CMOS process.

A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface

As FPGAs become more integrated into high-speed systems, high performance I/O with excellent signal integrity becomes more important. This paper describes how these challenges were met on an FPGA developed to support 1.6 Gbps differential source-synchronous standards and 300 MHz external memory interfaces. The I/O buffer features programmable drive strength, output impedance matching, hot-socketing compliance, and 3.3v tolerance. High-speed performance was achieved using design techniques of differential level-shifters with voltage and temperature compensated current sources, on-chip decoupling capacitors, and floating-well output buffers. In addition, DLLs and programmable phase offset circuits were used to obtain precise timing control. The chip was manufactured on a 90 nm CMOS process.