Chien-Chang Peng

Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block

In this paper, we propose a reliable low-power multiplier design by adopting algorithmic noise tolerant (ANT) architecture with the fixed-width multiplier to build the reduced precision replica redundancy block (RPR). The proposed ANT architecture can meet the demand of high precision, low power consumption, and area efficiency. We design the fixed-width RPR with error compensation circuit via analyzing of probability and statistics. Using the partial product terms of input correction vector and minor input correction vector to lower the truncation errors, the hardware complexity of error compensation circuit can be simplified. In a 12×12 bit ANT multiplier, circuit area in our fixed-width RPR can be lowered by 44.55% and power consumption in our ANT design can be saved by 23% as compared with the state-of-art ANT design.

A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design

Soft-error interference is a crucial design challenge in the advanced CMOS VLSI circuit designs. In this paper, we proposed a SEU Isolating DICE latch (Iso-DICE) design by combing the new proposed soft-error isolating technique and the inter-latching technique used in the DICE (Calin et al., 1996 [1]) design. To further enhance SEU-tolerance of DICE design, we keep the storage node pairs having the ability to recover the SEU fault occurring in each other pair but also avoid the storage node to be affected by each other. To mitigate the interference effect between dual storage node pairs, we use the isolation mechanism to resist high energy particle strikes instead of the original interlocking design method. Through isolating the output nodes and the internal circuit nodes, the Iso-DICE latch can possess more superior SEU-tolerance as compared with the DICE design (Calin et al., 1996 [1]). As compared with the FERST design (Fazeli, 2009 [2]) which performs with the same superior SEU-tolerance, the proposed Iso-DICE latch consumes 50% less power with only 45% of power delay product in TSMC 90nm CMOS technology. Under 22nm PTM model, the proposed Iso-DICE latch can also perform with 11% power delay product saving as compared with the FERST design (Fazeli, 2009 [2]) that performs with the same superior SEU-tolerance.

Near-threshold-voltage circuit design: The design challenges and chances

NTV is a new low power design concept for the pursuit of the highest power usage efficiency. The characteristics for each logic family are quite different under NTV while comparing to its operation under normal supply voltage. The circuit/architecture design policy under NTV is also different from its normal supply voltage operation. Process variation, performance degradation, and noise-interference are the three major design challenges in NTV design. In this paper, some effective candidate design solutions are presented to overcome these crucial NTV issues.

A high-speed, high fan-in dynamic comparator with low transistor count

In this article, we proposed a high-speed, high fan-in dynamic CMOS comparator with low transistor count. Our approach is to construct the dynamic comparator based on the prior superiority of dynamic CMOS comparator and to further enhance its operating speed. Constructing the comparator with dynamic CMOS architecture, we can save 63.2% transistor count as compared with the conventional static CMOS design. The main contribution to accelerate the speed of dynamic comparator is to solve the problem of ‘weak 0’ existing in the PMOS of pull-down network. Instead, as an alternate to PMOS in the pull-down network, we use NMOS combined with an additional inverter in the front of the NMOS input gate. In this way, we can perform the same function as PMOS, but transmitting with both ‘good 1’ and ’good 0’. As a result, the proposed dynamic comparator can operate with lower propagation delay in the pull-down network. Finally, the proposed 64-bit dynamic comparator circuit can operate correctly under a clock frequency of 450 MHz with 0.18 µm technology while the prior circuit can only operate under 250 MHz at the same time.

Robust C-element Design for Soft-Error Mitigation

C-element is a widely used component in soft-error tolerant designs to construct a robust soft-tolerant mechanism; however, C-element itself is not a robust device. In this paper, we proposed a robust C-element design by employing two transistors operating in saturation region parallel connected with C-element upper pMOS and lower nMOS to enhance its softerror tolerance. By utilizing the proposed C-element in the prior-art isolated latch designs, the maximum soft error tolerance can be improved by 25.87% as compared with conventional C-element.

Wide bandwidth and high precision power supply noise detector by using dual peak detection sample and hold circuits

In this paper, we proposed a high-performance, high-precision power supply noise PSN detector by using dual peak detection sample and hold circuits with source follower. By using dual peak detection sample and hold circuits, we can avoid PSN missing detection and therefore avoid massive PSN detection error. We also added one dummy switch to cancel the charge injection effect and to improve the PSN detection accuracy. In the proposed design, we applied one PMOS type charging circuit to enhance the operation frequency of differential amplifier, which can widen both the PSN detection bandwidth and the detection range. As a result, in the proposed PSN detection circuit, the PSN detection bandwidth can be raised from 1GHz to 2GHz with the PSN detection error lowered to ±3%. Moreover, the PSN detection range is widened from 10%-50%VDD to 5%-65%VDD as compared with the state-of-the-art design. Copyright

A PRECISE AND LINEAR POWER SUPPLY NOISE DETECTOR BY PROVIDING A STABLE CHARGING SOURCE

In this article, we proposed a noise detector with high linearity in CMOS 0.18um process. By removing the precharging capacitor and exchanging the connection of control signals, we can provide a stable charging voltage source to enhance power supply noise detection linearity from 0.9291 to 0.9986. By using separated supply voltage sources, we set the detection path with a higher supply voltage of 2.5V to turn on the detection circuitry immediately when supply voltage drops. In this way, the noise detection range can be enlarged and the noise detection accuracy can be enhanced. Finally, the power supply noise detection error can be lowered to 9.62%