I-Chyn Wey

Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits

As the size of CMOS devices is scaled down to nanometers, noise can significantly affect circuit performance. Because noise is random and dynamic in nature, a probabilistic-based approach is better suited to handle these types of errors compared with conventional CMOS designs. In this paper, we propose a cost-effective probabilistic-based noise-tolerant circuit-design methodology. Our cost-effective method is based on master-and-slave Markov random field (MRF) mapping and master-and-slave MRF logic-gate construction. The resulting probabilistic-based MRF circuit trades hardware cost for circuit reliability. To demonstrate a noise-tolerant performance, an 8-bit MRF carry-lookahead adder (MRF_CLA) was implemented using the 0.13-mum CMOS process technology. The chip measurement results show that the proposed master-and-slave MRF_CLA can provide a 7.00 times 10-5 bit-error rate (BER) under 10.6-dB signal-to-noise ratio, while the conventional CMOS_CLA can only provide 8.84 times 10-3 BER. Because of high noise immunity, the master-and-slave MRF_CLA can operate under 0.25 V to tolerate noise interference with only 1.9 muW/MHz of energy consumption. Moreover, the transistor count can be reduced by 42% as compared with the direct-mapping MRF_CLA design .

A scalable DCO design for portable ADPLL designs

A novel digital controlled oscillator (DCO) design methodology is presented in this paper. The new design methodology includes a scalable DCO architecture and the developed design flow. With precise analysis in early stage, the design effort of DCO can be reduced significantly. The proposed DCO architecture has the characteristics of high resolution, flexible operating range, and easy design. The design is suitable for a high performance clock generator in a system on chip (SoC) application.

A 0.18=μm Probabilistic-Based Noise-Tolerate Circuit Design and Implementation with 28.7dB Noise-Immunity Improvement

As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the injected noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. In this paper, we design and implement an 8-bit Markov random field carry lookahead adder (MRFCLA) probabilistic-based noise-tolerant circuit in 0.18μm CMOS process technology. This is the first working silicon design to prove the design concept of the noise-tolerant MRF circuits. The measurement results show that the proposed of the MRF adder can provide 28.7dB of noise-immunity as compared with its conventional CMOS design, when both circuits are facing the same server SNR environment. The MRF adder circuit can also achieve 10-6 BER when the supply voltage is only 0.45 V and SNR is only 10 dB.

Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error

In this paper, we propose a new error compensation circuit by using the dual group minor input correction vector to lower input correction vector compensation error. By utilizing the symmetric property of the minor input correction vector, the hardware complexity of the error compensation circuit can be lowered. By constructing the error compensation circuit mainly from the “outer” partial products, the hardware complexity only increases slightly as the multiplier input bits increase. In the proposed 16×16 bits fixed-width multiplier, the truncation error can be lowered by 87% as compared with the direct-truncated multiplier and the transistor count can be reduced by 47% as compared with the full-length multiplier. As compared with the state-of-the-art design, the proposed fixed-width multiplier performs not only with lower compensation error but also with lower hardware complexity, especially as multiplier input bits increase.

A new low-voltage CMOS 1-bit full adder for high performance applications

In this paper, a new low-voltage high-performance CMOS 1-bit full adder circuit is proposed. The new design is derived by combining XOR (XNOR) gates, used in the conventional full adder, and transmission gates. The proposed full adder can provide full voltage swing at a low supply voltage and offers superior performance in both power and speed than the conventional full adder, the transmission full adder, and the low-voltage full adder. Based on the simulation results performed by HSPICE, the new low-voltage design consumes minimal power and has a minimal power-delay product in the TSMC 0.35 /spl mu/m process, as supply voltage varies from 3.3 V to 2 V. Also, the new cell is demonstrated to consume minimal power as adopted in a 4/spl times/4 bit carry-save array adder, and a 4/spl times/4 bit pipelined carry-save array adder.

Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency

System-on-Chip (SoC) designs become more complex nowadays. The communication between each processing element often suffers challenges due to the wiring problem. Networks-on-Chip (NoC) provides a practical solution to solve the problem. The major components in NoC are routers, which are dominated by the buffer size. Previous mechanisms need large buffer size to achieve high performance. In this paper, a dynamic channel flow control mechanism is proposed to realize the channel resource sharing globally, which can increase the throughput and the channel utilization rate. An 8 × 8 mesh on-chip network is implemented on a cycle accurate simulator. By the experimental result, the proposed mechanism can reduce the buffer size by 30% as compared with virtual channel flow control at the same throughput. Moreover, the throughput can be improved by 20% as compared with wormhole flow control.

Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block

In this paper, we propose a reliable low-power multiplier design by adopting algorithmic noise tolerant (ANT) architecture with the fixed-width multiplier to build the reduced precision replica redundancy block (RPR). The proposed ANT architecture can meet the demand of high precision, low power consumption, and area efficiency. We design the fixed-width RPR with error compensation circuit via analyzing of probability and statistics. Using the partial product terms of input correction vector and minor input correction vector to lower the truncation errors, the hardware complexity of error compensation circuit can be simplified. In a 12×12 bit ANT multiplier, circuit area in our fixed-width RPR can be lowered by 44.55% and power consumption in our ANT design can be saved by 23% as compared with the state-of-art ANT design.

A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement

As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. However, probabilistic-based designs cost larger hardware area. In this paper, we design and implement a hardware-efficient probabilistic-based noise-tolerant circuit, an 8-bit Markov random field carry lookahead adder (MRF_CLA), in 0.13 mum CMOS process technology. The measurement results show that the proposed MRF_CLA can provide 24.5 dB of noise-immunity enhancement as compared with its conventional CMOS design. Moreover, the transistor count can be saved 42% as compared to the state-of-art MRF design [1].

A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design

Soft-error interference is a crucial design challenge in the advanced CMOS VLSI circuit designs. In this paper, we proposed a SEU Isolating DICE latch (Iso-DICE) design by combing the new proposed soft-error isolating technique and the inter-latching technique used in the DICE (Calin et al., 1996 [1]) design. To further enhance SEU-tolerance of DICE design, we keep the storage node pairs having the ability to recover the SEU fault occurring in each other pair but also avoid the storage node to be affected by each other. To mitigate the interference effect between dual storage node pairs, we use the isolation mechanism to resist high energy particle strikes instead of the original interlocking design method. Through isolating the output nodes and the internal circuit nodes, the Iso-DICE latch can possess more superior SEU-tolerance as compared with the DICE design (Calin et al., 1996 [1]). As compared with the FERST design (Fazeli, 2009 [2]) which performs with the same superior SEU-tolerance, the proposed Iso-DICE latch consumes 50% less power with only 45% of power delay product in TSMC 90nm CMOS technology. Under 22nm PTM model, the proposed Iso-DICE latch can also perform with 11% power delay product saving as compared with the FERST design (Fazeli, 2009 [2]) that performs with the same superior SEU-tolerance.

A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder

In this paper, a high speed, low latency pipelined Booth multiplier with new Manchester carry-bypass adder (MCBA) is proposed. By using new partial product generation scheme and new MCBA, the latency is reduced to 6. By using new MCBA, the speed bottleneck is overcome with 40.16% improvement and the energy can be saved with 30.59% improvement. The 13-bit new MCBA pipelined into 2 stages can operate above 1 GHz with worst-case delay of 0.833 ns and consumed only 16.81 mW. Finally, the proposed pipelined Booth multiplier is presented at 3.3 V, 1 GHz in TSMC 0.35 /spl mu/m process with a power consumption of only 60.18 mW.