Cihun-Siyong Alex Gong

Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0.18-

This paper presents the design and experimental evaluation of a new type of irreversible energy recovery logic (ERL) families called complementary energy path adiabatic logic (CEPAL). It inherits the advantages of quasi-static ERL (QSERL) family, but is with improved driving ability and circuit robustness. The proposed logic style features no hold phase compared to its QSERL counterpart under the same operation conditions; thereupon no feedback keeper is required so that considerable improvements in area and power overheads can be achieved. Moreover, its throughput becomes twice as high as that of QSERL when their frequencies of power clocks (PCs) are identical. Results on the impact of variation on CEPAL are provided. Comparison between CEPAL and other known low-power logic style achieving iso-performance, namely, subthreshold logic is also given. In order to demonstrate workability of the newly developed circuit, an 8-bit shift register, designed in the proposed techniques, has been fabricated in a TSMC 0.18-mum CMOS process. Both simulation and measurement results verify the functionality of such a logic, making it suitable for implementing energy-aware and performance-efficient very-large scale integration (VLSI) circuitry.

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In the fields of wireless bioelectronics implants and sensor network systems, amplitude shift keying (ASK) is one of the most commonly used schemes employed to modulate the baseband signal with reference to the intermediate or even the carrier frequency. In this study, a demodulator architecture capable of dealing with most of the previous limitations in an ASK-utilized medical implant, especially in want of being powered through wireless delivering, is proposed. It features the abilities of working on a very small modulation index and being provided without any R/C component(s) inside by means of a self-sampling scheme. The design has been implemented in an 18-mum CMOS process. The demodulator circuit occupies a die size of merely 32.3 times 14.5 mu m2. Analytic results from both simulated gradation and fabricated chips show that the proposed circuit can operate at a carrier of 2 MHz and achieve a modulation rate of up to 50%. The results also demonstrate that the presented work can still perform a proper demodulation even with a modulation index beneath 5.5%. An average power of approximately 336 muW was confirmed in return for the remarkable advantages. All aspects regarding the design, including a review of the prior arts, system consideration, circuit description, and analyses from simulation phase to actual measurement, are presented in detail.

m CMOS

This paper describes a low-noise and low-power architecture of the differential difference amplifier (DDA) for neural recording system. The proposed neural amplifier combines DC offset rejection and low-frequency cutoff tuning without off-chip components. DC offset rejection is carried out by ac coupling which is realized by series connection of a capacitor and a MOS-bipolar pseudoresistor. Low-frequency cutoff tuning permits recording local field potential or neural action potential. Frequency tuning mechanism depends on the feedback capacitor and floating tunable resistor which constructs a low frequency pole nearby 100 Hz. The proposed design is in TSMC 0.18 mum 1P6M CMOS process, which achieves gain of 40.8 dB, passband from 107 Hz to 10.3 kHz, input-referred noise of 4.83 muVrms, power consumption of 25.9 muW, and 0.084 mm2 of chip area.

A Truly Low-Cost High-Efficiency ASK Demodulator Based on Self-Sampling Scheme for Bioimplantable Applications

This study demonstrates a wide frequency tuning range LC voltage-controlled oscillator (LC-VCO) with an active inductor in a 90-nm CMOS process. As the proposed LC-VCO is intended to be extremely flexible without redesign for several new-generation SerDes interfaces, a wide operating frequency makes the phase-locked loop (PLL) applicable to the multistandards. To demonstrate a highly competitive design, a quality (Q) factor enhancement technique has been also demonstrated to reduce the loss from the active inductor, leading to an appropriate phase noise over the entire tuning range. At a supply of 1.2 V, the fabricated LC-VCO provides a frequency tuning range of 0.9-8 GHz (160%) with power consumption of 3.2-19.1 mW. The measured phase noise is from -105 to -118 dBc/Hz at a 1-MHz offset. Realized in a fully integrated PLL chip, it occupies an active area of 0.08 × 0.16 mm2.

A differential difference amplifier for neural recording system with tunable low-frequency cutoff

A fully integrated CMOS rectifier, intended for inductively powered electronic implants and featuring ultra-low-loss characteristic, is presented. By making use of high-performance active diodes fulfilling almost ideal switching (zero forward voltage drop) and circuit to be provided with negative resistance, the proposed design is able to achieve an maximum conversion efficiency of more than 90% when designed in a 0.18-mum standard CMOS process, without any special device requiring additional manufacturing procedures. As a result, the proposed design dramatically reduces the production cost. Estimations in all aspects regarding the performance of the rectifier are given in this paper.

A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes

A complementary energy path adiabatic logic (CEPAL) designed for ubiquitous large-scaled digital systems achieves higher noise immunity, higher driving ability, and reduced power density than the prior quasi-static structure. By applying CEPAL to the clocked storage elements (i.e. DFFs) with a diode-shared scheme, the overall efficiency is dramatically improved without increasing the design overhead compared with the quasi-static implementation. A test module consists of an 8-bit CEPAL shift register (SFR) has been laid out in a 0.18-μm CMOS process. Post-layout analytic results, including parasitic effect and exhibiting the benefits of various aspects in the proposed fashion, are given as proof of concept.

Efficient CMOS rectifier for inductively power-harvested implants

This paper presents novel approaches for higher-resolution, higher output gain, better-linearity, and less-power-consumption micro-stimulator array. To achieve higher output gain for more ideal stimulus current without extra cascode stage, a gain-boosting design is adopted. To achieve higher-resolution and better linearity, a continuous pulse-width modulation-based conversion architecture has been proposed. To overcome extra power consumption of the baseband control logic, the energy recovery scheme is also applied. A monolithic circuitry of this efficient stimulator array has been realized by using TSMC 0.18-mum 1P6M standard CMOS technology and the experimental results show improvement over the prior approaches.

Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications

In this study, a monolithic system is proposed and verified for retinal prosthesis. It includes an extraocular platform which can support a 16-channel image processing with parameter control and a channel-combined Manchester encoder for wireless transmission. Besides, an intraocular programme-controlled chip for multi-channel microstimulator is also presented. This micro-control chip has been realized by using a TSMC 0.35-mum 2P4M standard CMOS technology. The results of extraocular testing show that the efficacy of the system can meet the requirement of an implantable device for the retinal prosthesis.

An Efficient Micro-Stimulator Array Using Unitary-Size DAC With Adiabatic Baseband Scheme

This paper describes an ADC architecture termed pseudo-flash ADC and intended for biomedical sensing applications. It features high conversion speed which is the same as that of flash ADC, but has significantly lower hardware implementation overhead. Designed in a 0.18-mum standard CMOS technology in accordance with a specification of 250 KSamples/s and 6-bit resolution, the proposed ADC architecture consumes a total of nearly 290 muWunder the nominal supply voltage of 1.8 V, without the requirement of a large number of comparators as compared with the conventional flash ADC architecture.

Design And Implementation Of A Monolithic Programme-Controlled System For Retinal Prosthesis

Read stability has been considered one of the dominant factors governing the overall performance and operation limitation of static random access memory (SRAM). Furthermore, periodic precharge in read/write (R/W) cycle is the major source of power consumption in an SRAM circuit. To address these two concerns, a newly developed SRAM architecture, with specific concentration on read operation, is described in this paper. By utilizing a ldquopreequalizerdquo scheme, direct connections of the bit lines to power-supply nodes at the beginning of read cycle no longer exist, thereby having the SRAM be provided with an improved power efficiency. The preequalize scheme also yields an increased read static noise margin (SNM) and a cell area comparable to that of the conventional counterpart, due to the similarity between the proposed SRAM cell and familiar inverter circuit in geometry (aspect) ratios of the transistors involved. Several concerns stemming from the proposed scheme are discussed. A 4-kb-capacity prototype designed in a 0.18-mum CMOS process achieves a more power-efficient operation as compared to that adopting conventional architecture.