Hwang-Cherng Chow

Bidirectional buffer for mixed voltage applications

A succinctest design of a mixed voltage bidirectional buffer in the literature is proposed for interface applications. By employing a floating N-well circuit technique, two series PMOS transistors are used as an active pull-up driver. Such a structure provides a simple circuit that requires only a single terminal pad, a single power supply, and is free of DC leakage current. Mixed voltage interface applications such as 3.3 V/5 V, 2.5 V/3.3 V and 5 V/12 V are demonstrated.

High performance automatic gain control circuit using a S/H peak-detector for ASK receiver

A high performance automatic gain control (AGC) circuit is proposed in this paper. The proposed AGC incorporates a modified sample and hold peak-detector. Circuit operation of this new peak-detector demonstrates superior performance to the conventional one, by keeping and tracking the peak of the input signal at the same time. In addition, the design complexity of the proposed AGC is reduced in both the low pass filter and the demodulator due to the modified peak-detector. Based on simulation results, the complete AGC loop shows very satisfactory circuit operation. Therefore, it is suitable for high performance communication applications such as ASK (amplitude shift keyed) receivers.

High CMRR instrumentation amplifier for biomedical applications

A new low-voltage single-power high CMRR and PSRR instrumentation amplifier is developed for biomedical applications. The proposed circuit uses a new structure to solve the conventional circuitspsila problems. Under similar conditions for comparison, the simulation results show the proposed circuits have better performances than conventional circuits. Besides, we also present a level shifting circuit for biomedical applications. The overall proposed circuits by HSPICE using UMC 0.18 um CMOS technology achieve a very high CMRR up to 160 dB and PSRR up to 110 dB at 1.8 V single power supply.

An analytical CMOS inverter delay model including channel-length modulations

An analytical delay model of a CMOS inverter that includes channel-length modulation and source-drain resistance as well as high-field effects is introduced. This model is based on the improved short-channel MOSFET model derived from a quasi-two-dimensional analysis of operation in the saturation region. Calculations of the rise, fall, and delay times show good agreement with SPICE MOS level three simulations. >

High performance sense amplifier circuit for low power SRAM applications

A high performance sense amplifier (SA) circuit for low power SRAM applications is presented in this paper. The transistor stage number of the proposed SA from VDD to GND is reduced for fast low voltage operation. Thus the proposed sense amplifier which is implemented in 0.35 /spl mu/m CMOS process can work at 100 MHz with voltage as low as 1V. The improvement of sensing delay is 6-14% for various output loading. As the proposed SA works at 3.3 V, the simulations show that this design has 14% and 63% power delay product improvement over the prior art and conventional sense amplifier, respectively.

A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications

A new self-timed timing control and WRV (without reference voltage) algorithm based on the conventional SA-ADC architecture to detect biomedical signals is proposed in this paper. Using the new self-timed control method, the conversion time could be shortened to turn off the analog circuit earlier to lower the power consumption. In addition, a new WRV algorithm is introduced to remove the circuits of reference voltage sources in the DAC sub-circuit inside the SA-ADC. By this way, both INL and DNL errors of this SA-ADC are well controlled in 0.33LSB from simulation results. Also, the input range of this proposed SA-ADC can be extended to rail-to-rail.

Low power LVDS circuit for serial data communications

With the advanced process, the supply voltage is decreased and power consumption is reduced dramatically. However, the power supply of LVDS receiver side is constrained, because the common mode voltage of LVDS is between 0.1 V and 2.4 V. By combining with design concepts of prior arts related to 1.8 V receiver circuit, a fully function of low power and high speed LVDS circuit is achieved. This presented LVDS transceiver has several advantages including easy to use and low power. The power consumption per unit without clock driver is only 8.68 mW/GHz, which has improved the performance by 38.2%. Due to the lower supply voltage of the receiver circuit, the power consumption per unit is 3.97 mW/GHz, with improvement of 134%. Besides, hysteresis circuit in this proposed circuit provides a better noise margin.

A new low-voltage CMOS 1-bit full adder for high performance applications

In this paper, a new low-voltage high-performance CMOS 1-bit full adder circuit is proposed. The new design is derived by combining XOR (XNOR) gates, used in the conventional full adder, and transmission gates. The proposed full adder can provide full voltage swing at a low supply voltage and offers superior performance in both power and speed than the conventional full adder, the transmission full adder, and the low-voltage full adder. Based on the simulation results performed by HSPICE, the new low-voltage design consumes minimal power and has a minimal power-delay product in the TSMC 0.35 /spl mu/m process, as supply voltage varies from 3.3 V to 2 V. Also, the new cell is demonstrated to consume minimal power as adopted in a 4/spl times/4 bit carry-save array adder, and a 4/spl times/4 bit pipelined carry-save array adder.

1V 10-bit successive approximation ADC for low power biomedical applications

A low power 1 V 10-bit successive approximation analog-to-digital converter (SA-ADC) is presented for biomedical applications. In the DAC capacitor arrays of this SA-ADC a charge-recycling method for switching the capacitors is used. Besides, a 1 V rail-to-rail input comparator with both current driven bulk technique and offset cancellation is proposed. The complete 1 V ADC implemented in TSMC 0.18 um CMOS process has a signal-to-noise ratio of 58.5 dB and its effective number of bits is 9.4 based on post-layout simulations. The entire ADC power consumption is 32.6 uW for normal signals and 29.5 uW for ECG applications.

A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering Applications

In this paper, a 1 volt rail-to-rail input range amplifier has been proposed. In the amplifier design, the current driven bulk (CDB) technique is adopted to reduce threshold voltages of input devices to eliminate the conventional dead zone problem. The performance results of the proposed 1 volt low power amplifier are input rail-to-rail with gain at 71 dB and CMRR at 100 dB. We use the proposed amplifier to implement a low pass filter for biomedical signal applications. Simulation results for an electrocardiograph (ECG) signal are very satisfactory. The total harmonic distortion of the low pass filter is -30 dB. Besides, the programmable cut-off frequency of the bio-signal low pass filter is provided for use.