Chien-I Kuo

InAs Thin-Channel High-Electron-Mobility Transistors with Very High Current-Gain Cutoff Frequency for Emerging Submillimeter-Wave Applications

60 nm InAs high-electron-mobility transistors (HEMTs) with a thin channel, a thin InAlAs barrier layer, and a very high gate stem structure have been fabricated and characterized. The thickness of the channel, as well as that of the InAlAs barrier layer, was reduced to 5 nm. A stem height of 250 nm with a Pt-buried gate was used in the device configuration to reduce the parasitics. A high DC transconductance of 2114 mS/mm and a current-gain cutoff frequency (fT) of 710 GHz were achieved at VDS=0.5 V.

Investigation of Impact Ionization in InAs-Channel HEMT for High-Speed and Low-Power Applications

An 80-nm InP high electron mobility transistor (HEMT) with InAs channel and InGaAs subchannels has been fabricated. The high current gain cutoff frequency (ft) of 310 GHz and the maximum oscillation frequency (fmax) of 330 GHz were obtained at VDS = 0.7 V due to the high electron mobility in the InAs channel. Performance degradation was observed on the cutoff frequency (ft) and the corresponding gate delay time caused by impact ionization due to a low energy bandgap in the InAs channel. DC and RF characterizations on the device have been performed to determine the proper bias conditions in avoidance of performance degradations due to the impact ionization. With the design of InGaAs/InAs/InGaAs composite channel, the impact ionization was not observed until the drain bias reached 0.7 V, and at this bias, the device demonstrated very low gate delay time of 0.63 ps. The high performance of the InAs/InGaAs HEMTs demonstrated in this letter shows great potential for high-speed and very low-power logic applications.

InAs High Electron Mobility Transistors with Buried Gate for Ultralow-Power-Consumption Low-Noise Amplifier Application

An InAs/In0.7Ga0.3As composite channel high-electron-mobility transistor (HEMT) fabricated using the gate sinking technique was realized for ultralow-power-consumption low-noise application. The device has a very high transconductance of 1900 mS/mm at a drain voltage of 0.5 V. The saturated drain–source current of the device is 1066 mA/mm. A current gain cutoff frequency ( fT) of 113 GHz and a maximum oscillation frequency ( fmax) of 110 GHz were achieved at only drain bias voltage Vds = 0.1 V. The 0.08 ×40 µm2 device demonstrated a minimum noise figure of 0.82 dB and a 14 dB associated gain at 17 GHz with 1.14 mW DC power consumption.

30-GHz Low-Noise Performance of 100-nm-Gate-Recessed n-GaN/AlGaN/GaN HEMTs

We demonstrate a 100-nm-gate-recessed n-GaN/AlGaN/GaN high-electron mobility transistor (HEMT) with low-noise properties at 30 GHz. The recessed GaN HEMT exhibits a low ohmic-contact resistance of 0.28 ¿·mm and a low gate leakage current of 0.9 ¿A/mm when biased at VGS = -3 V and VDS = 10 V. At the same bias point, a minimum noise figure of 1.6 dB at 30 GHz and an associated gain of 5 dB were achieved. To the best of our knowledge, this is the best noise performance reported at 30 GHz for gate-recessed AlGaN/GaN HEMTs.

Novel Metamorphic HEMTs With Highly Doped InGaAs Source/Drain Regions for High Frequency Applications

In this paper, we report the first result of a strained In_0.52Ga_0.48 As channel high-electron mobility transistor (HEMT) featuring highly doped In_0.4Ga_0.6 As source/drain (S/D) regions. A lattice mismatch of 0.9% between In_0.52Ga_0.48 As and In_0.52Ga_0.48 As S/D has resulted in a lateral strain in the In_0.52Ga_0.48 As channel region, where the series resistance is reduced with highly doped S/D regions. An experimentally validated device simulation is advanced for the proposed HEMT, and the results of this paper have shown that there are 60% drive-current and 100% transconductance improvements, compared with the conventional structure. A remarkable 150-GHz increase in the cutoff frequency has been seen for the proposed structure over the conventional one as well for the shown devices.

InAs Channel-Based Quantum Well Transistors for High-Speed and Low-Voltage Digital Applications

High-performance indium arsenic (InAs) channel-based quantum well field-effect transistors (QWFETs) have been fabricated. A superior drain-source current density of 1015 mA/mm was achieved, with a high transconductance of 1900 mS/mm when the drain (V DS ) was biased at 0.5 V. The current gain cutoff frequency (f T ) and maximum oscillation frequency (f max ) were extracted to be 393 and 260 GHz, respectively. A very low gate delay of 0.54 ps was also achieved at a 0.5 V drain bias. Compared to a silicon n-channel metal-oxide semiconductor field-effect transistor, the QWFETs exhibited a better radio-frequency performance with lower dc power consumption, which indicates the great potential for high-speed and low-voltage digital applications.

RF and logic performance improvement of In0.7Ga0.3As/InAs/In0.7Ga0.3As composite-channel HEMT using gate-sinking technology

Eighty-nanometer-gate In0.7Ga0.3As/InAs/In0.7Ga0.3As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250degC for 3 min, the device exhibited a high gm value of 1590 mS/mm at Vd = 0.5 V, the current-gain cutoff frequency fT was increased from 390 to 494 GHz, and the gate-delay time was decreased from 0.83 to 0.78 ps at supply voltage of 0.6 V. This is the highest fT achieved for 80-nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device.

Two-dimensional to three-dimensional tunneling in InAs/AlSb/GaSb quantum well heterojunctions

We examine room temperature band-to-band tunneling in 2D InAs/3D GaSb heterostructures. Specifically, multi-subband, gate-controlled negative differential resistance is observed in InAs/AlSb/GaSb junctions. Due to spatial confinement in the 10 nm-thick InAs layer, tunneling contributions from two distinct subbands are observed as sharp steps in the current-voltage characteristics. It is shown that the relative position of the steps can be controlled via external gate bias. Additionally, the extracted separation in the subband energy agrees well with the calculated values. This is the first demonstration of a gate controlled tunneling diode with multiple subband contributions.

Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support

A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nm-thin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hydrogen silsesquioxane is used as a novel mechanical support structure to suspend the 10-nm-thin InAs drain with enough undercut to be able to demonstrate an overlap gate architecture. The overlap gate InAs/AlSb/GaSb TFET shows an ON current density of 22 μA/μm2 at VGS = VDS = 0.4 V and the subthreshold slope is 194 mV/decade at room temperature and 46 mV/decade at 100 K.

RF and Logic Performance Improvement of Composite-Channel HEMT Using Gate-Sinking Technology

Eighty-nanometer-gate In0.7Ga0.3As/InAs/In0.7Ga0.3As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250degC for 3 min, the device exhibited a high gm value of 1590 mS/mm at Vd = 0.5 V, the current-gain cutoff frequency fT was increased from 390 to 494 GHz, and the gate-delay time was decreased from 0.83 to 0.78 ps at supply voltage of 0.6 V. This is the highest fT achieved for 80-nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device.