Chih-Chang Cheng

State-of-the-art device in high voltage power ICs with lowest on-state resistance

High performance LDMOS of 600–800V Vbdss has been developed with PB (Pbody)_Extension RESURF scheme for smart power applications. This device design demonstrates the lowest specific on-state resistance against to the latest publications (40% improvement than triple RESURF, 65% improvement than double RESURF in JI LDMOSFET) in 600–800V families and breaks 1-D silicon limit. This technology also surpasses the performance in thin SOI technology, yet it uses the bulk Si material and less manufacturing processing steps.

A 700-V Device in High-Voltage Power ICs With Low On-State Resistance and Enhanced SOA

This paper presents a 700-V high-voltage laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with a p-body_Extension reduce surface field (RESURF) structure. Experimental results demonstrate that the low ON resistance and breakdown voltage (BV)- RON,sp figure of merit approach the ideal Baligas power law, in addition, breaks the quasi-saturation limitation with enhanced device safe operating area (SOA). The optimal charge balance and geometrical design to achieve the lowest specific ON resistance (RON,sp) with the desired maximum high BV are displayed and discussed by simulations and experimental results. The 2-D simulations confirmed that, compared with conventional triple-RESURF structures, the presented device provides a fourfold reduction in the surface electric field on the source side and a 32% improvement in blocking voltage. The specific ON resistance demonstrates superior 40% lower performance than published Junction Isolation LDMOS device families. In addition, its twofold increase in SOA extension can improve the performance of circuit designs for switching power supply applications.

0.18 µm BCD technology platform with best-in-class 6 V to 70 V power MOSFETs

This paper presents a single BCD technology platform with high performance power devices at a wide range of operating voltages. The platform offers 6 V to 70 V LDMOS devices. All devices offer best-in-class specific on-resistance of 20 to 40 % lower than that of the state-of-the-art IC-based LDMOS devices and robustness better than the square SOA (safe-operating-area). Fully isolated LDMOS devices, in which independent bias is capable for circuit flexibility, demonstrate superior specific on-resistance (e.g. 11.9 mΩ-mm2 for breakdown voltage of 39 V). Moreover, the unusual sudden current enhancement appeared in the ID-VD saturation region of most of the high voltage LDMOS devices is significantly suppressed.

Design of 700V LIGBT with the suppressed substrate current in a 0.5um junction isolated technology

In this paper, a 700V lateral insulated gate bipolar transistor (LIGBT) design is proposed in a junction-isolated technology. Several key properties of LIGBT, such as hole injection leakage and breakdown-voltage, are investigated by using two-dimensional numerical simulator, MEDICI. To improve vertical junction isolation capability, an extra BLN (Buried-Layer N-type) layer is inserted in-between the BLP (Buried-Layer P-type) and the P-substrate, to enhance hole potential barrier and to block substrate leakage as well as to ensure high breakdown voltage (>;700V). An optimized LIGBT with high breakdown-voltage, very low substrate-leakage (<;0.1uA/um), and low switching turn-off time, are presented and analyzed.