Chih-Da Chien

A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications

A multi-standard (JPEG/MPEG-1/2/4/H.264) video decoder includes 252kgates and 4.9kB internal memory in a core size of 4.2times1.2mm 2 using 0.13mum 1P8M CMOS. The power consumption at 1.2V supply is 71 mW at 120MHz for real-time HD1080 and 7.9mW at 20MHz for real-time H.264 decoding of D1 video

A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications

This paper presents a high performance VLSI architecture design for MPEG-4 AVC/H.264 CAVLC encoding. In the proposed design, we propose a forward-based parallel coding (FPC) technique to increase the data throughput rate. Moreover, two approaches called arithmetic table elimination (ATE) and fast look-up table matching (FLM) are exploited to reduce the hardware cost. With the synthesis constraint of 125 MHz clock, the hardware cost of the proposed design is 9724 gates based on a 0.18mum CMOS technology, which achieves the real-time processing requiremenwat for H.264 video encoding on HD1080 format video

An Area-Efficient Variable Length Decoder IP Core Design for MPEG-

This paper proposes an area-efficient variable length decoder (VLD) IP core design for MPEG-1/2/4 video coding applications. The proposed IP core exploits the parallel numerical matching in the MPEG-1/2/4 entropy decoding to achieve high data throughput rate in terms of limited hardware cost. This feature not only improves the performance of VLD, but also facilitates reducing the power consumption through lowering down the supply voltage while maintaining enough data throughput rate. Moreover, we propose a partial combinational component enabling approach for minimizing the power consumption of the proposed design. Based on 0.18-mum CMOS technology, the implementation results show that the proposed IP core operates at 125-MHz clock frequency with the cost of 13 105 gates. In addition, the power consumption of the proposed design reaches 163.4 muW operated at 12.5 MHz with 0.9-V supply voltage, which is fast enough for MPEG-1/2/4 real-time decoding on 4CIF video@30 Hz. Compared to the existing designs, the proposed IP core possesses both higher data throughput and less hardware cost

hbox 1/2/4

The dynamic memory controller plays an important role in system-on-a-chip (SoC) designs to provide enough memory bandwidth through external memory for DSP and multimedia processing. However, the overhead cycles in accessing the data located in external memory have much influence on the SoC performance. In this paper, we propose a low latency memory controller with AHB interface to reduce the overhead cycles for the SDR memory access in the SoC designs. Through the pre-calculated addresses of impending transfers, two memory control schemes, i.e. Burst terminates Burst (BTB) and Anticipative Row Activation (ARA), are used to reduce the latency of SDR memory access. The experimental results show that the proposed memory controller reduces the memory bandwidth by 33% in a typical MPEG-4 video decoding system.

Video Coding Applications

The proposed IP core design design exploits an adder-based quarter-pixel filter optimized by data sharing for low cost consideration. This optimization reduces over 87% of hardware complexity as compared to the quarter-pixel filter in the existing design (Wang, J.X. et al. Proc. IEEE ASIC Conf., vol.2, p.942-5, 2003). In addition, we propose a low-power design technique called dynamic partially guarded computation (DPGC) to reduce the power consumption on pixel interpolation. After applying the DPGC, we obtain 60% reduction in the power consumption of the interpolation operations in the proposed design. Using a 0.18 /spl mu/m CMOS technology, the proposed design achieves real-time processing of MPEG-1/2/4 decoding on 4CIF video when operated at 54 MHz. In addition, the proposed design has been integrated into a MPEG-4 video decoder for system verification through a XILINX multimedia FPGA board.

A Low Latency Memory Controller for Video Coding Systems

This article proposes a low-cost, low-power multistandard video decoder for high definition (HD) video applications. The proposed design supports multiple-standard (JPEG baseline, MPEG-1/2/4 Simple Profile (SP), and H.264 Baseline Profile (BP)) video decoding through interactive parsing control and common parameter bus interface. In order to reduce hardware cost, the shared adder-based structure and reusable data management are proposed to achieve hardware sharing and reduce internal memory size, respectively. In addition, the proposed design is optimized through reducing memory bandwidth by increasing both data reuse amount and burst length of memory access as well as eliminating cycle overhead in data access for supporting HD video decoding with single AHB-based SDR memory. The proposed 252Kgates/4.9kB/71mW/0.13μm multi-standard video decoder reduces 72% in gate count and 87% in power consumption as compared to the state-of-the-art design, when operating at 120MHz for real-time HD1080 video decoding with single AHB-based SDR memory.

A low-power motion compensation IP core design for MPEG-1/2/4 video decoding

Entropy coding is one of the main techniques for lossless data compression in many multimedia applications. In video and image coding standards such as JPEG, MPEG1/2/4, and H.26x, the most often used entropy coding techniques include run-length coding and variable-length coding. Due to the demands of high quality video compression like DTV or HDTV, the complexity of entropy coding increases significantly. This fact motivates the design of the high performance entropy decoder proposed in this paper. The proposed IP core exploits the concurrent operations in the MPEG4 entropy decoding to achieve high performance in terms of limited hardware cost. The implementation results show that the proposed IP core operates at 125 MHz clock frequency (i.e. 2000 Mbit/s) with the cost of 0.22 mm/sup 2/ silicon area based on a 0.25 um CMOS technology.

A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications

This paper presents a new low-power parameterized hardware design for the one-dimensional (1D) discrete Fourier transform (DFT) of variable lengths. By combining the cyclic convolution formulation, block-based distributed arithmetic (BDA), and Cooley–Tukey decomposition algorithm together, we have developed a parameterized hardware design for the DFT of variable lengths ranging from 256 to 4096 points and with different modes of performance. The proposed design can perform different lengths of DFT computation through the configuration of parameters, which not only provides the flexibility in computing different length DFT but also facilitates the performance-driven design considerations in terms of power consumption and processing speeds, that is, we can configure the proposed design in different modes of performance by setting different parameters. This feature is beneficial to developing a parameterized DFT soft Intellectual Property (IP) core or hard IP core for meeting the system requirements of different silicon-on-a-chip (SOC) applications as compared with the existing fixed length DFT designs.

A high-performance MPEG4 bitstream processing core

In this paper we propose a memory-based hardware accelerator for MPEG-4 audio coding and reverberation to achieve both high quality and reality of audio. The proposed design can realize both the computation-intensive component of 256/2048-point IMDCT and the 1024-point FFT-based reverberation through the same hardware engine by adopting a unified IMDCT/FFT/IFFT algorithm, which greatly reduces the hardware cost. The proposed design can achieve both the real-time 5.1 channel audio decoding at the sampling rate of 44.1 KHz and audio reverberation with the hardware cost of 26,633 gates and 4.6K words of local memory for storing transform coefficients and temporary results. The maximum working frequency achieves 220 MHz when implemented by UMC 0.18mum CMOS technology, which can fit the real-time processing requirement of many high quality MPEG-4 audio coding applications

A LOW-POWER PARAMETERIZED HARDWARE DESIGN FOR THE ONE-DIMENSIONAL DISCRETE FOURIER TRANSFORM OF VARIABLE LENGTHS

This paper presents a power-aware IP core generator for the 1D DFT design. We optimize the proposed DFT IP design both in algorithm and architecture levels for achieving low hardware complexity. In algorithm level, we first use radix-2/sup c/ algorithm to split a length-N DFT into multiple length-N/2/sup c/ DFTs for facilitating computation sharing between parallel DFT outputs. Then, we formulate the length-N/2/sup c/ DFT into cyclic convolution form to facilitate the hardware cost reduction. In architecture level, we implement the design with a filter-based architecture optimized by a bit-level sub-expression sharing. In addition, we have applied the power-aware design concept in the proposed IP core generator through trading off the power consumption, data precision, and hardware cost in the design phase by parameter configurations through graphic user interface.