Chih-Fang Huang

Effects of Gate Field Plates on the Surface State Related Current Collapse in AlGaN/GaN HEMTs

During off-state, the influence of surface-trapped electron charges induced by high-field stress near the gate electrode of AlGaN/GaN power high-electron mobility transistor devices causes a reduction in two-dimensional electron gas (2DEG) carrier density at the heterointerface. In a pulse turn-on operation, the weakened 2DEG channel results in a higher on-state conduction resistance during the transient, known as the current collapse phenomenon. The phenomenon increases the switching loss by a higher on-state resistance and prolonged turn-on transition time, thus limits the device operating frequency range. In this paper, such a phenomenon is modeled, analyzed by Sentaurus TCAD simulation, and verified by the laboratory measurement data, with the emphasis on the influence of field plates toward the current collapse. The spatial distributions of trapped electrons and excess free electrons along the AlGaN surface are modeled and analyzed to arrive at the quantitative relationships among the trapped electron density, on-resistance increase, and the electric field distribution which provide a reliable criterion for current collapse reduction. It was found that, with a proper field plate design, it is possible to achieve an improvement on transient on-state resistance and the current recovery time.

6.5 V High Threshold Voltage AlGaN/GaN Power Metal-Insulator-Semiconductor High Electron Mobility Transistor Using Multilayer Fluorinated Gate Stack

In this letter, the approach of partial AlGaN recess and multiple layers of fluorinated Al2O3 gate dielectric is utilized to achieve highest reported positive gate threshold voltage (VTH) without severe reduction on 2-D electron gas carrier mobility in AlGaN/GaN HEMTs. Guided by the design and verification through analytical model, proper fluorine ions incorporation is made through fabrication. The approach resulted in a high VTH of +6.5 V and competitive drain saturation current (IDMAX) of 340 mA/mm. Furthermore, low gate leakage current and high breakdown voltage of 1140 V were also demonstrated.

Electrical Characteristics of

In this letter, electrical characteristics of nanolaminate Al₂ O₃/TiO₂/Al₂O₃ on <i>p</i>-GaN MOS capacitor with and without PMA and (NH₄)₂ S_X treatments were investigated. I-V and C-V characteristics were improved by both PMA and (NH₄)₂S_X treatments. The leakage-current densities can be improved to 3.0 × 10^-8 and 2.2 × 10^-8 A/cm² at ±1 V, respectively. Almost an ideal C-V curve, the effective dielectric constant of 12.1 and the averaged D_it value of 4.3 × 10¹¹ eV^-1 · cm^-2 were obtained.

\hbox{Al}_{2} \hbox{O}_{3}/\hbox{TiO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}

This paper reports extensive modelling and analysis of the temperature dependence on the device characteristics of the AlGaN/GaN high electron mobility transistors (HEMTs). A physics-based model is proposed in this study in order to correctly predict the gate flat-band Schottky barrier height, energy band Fermi-level (EC–EF) at the AlGaN/GaN interface, two-dimensional electron gas sheet density, gate threshold and (ID–VG) at sub-threshold voltages, and drain current–voltage (ID–VD) characteristics under various high-temperature conditions. The analytical results are then verified by comparing with the laboratory measurement as well as the numerical results obtained from the Sentaurus TCAD simulation. The proposed model is found to be useful for power electronic device designers on the prediction of the AlGaN/GaN HEMT device performance under high-temperature operation.

Nanolaminate MOS Capacitor on

This paper presents a 700-V high-voltage laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with a p-body_Extension reduce surface field (RESURF) structure. Experimental results demonstrate that the low ON resistance and breakdown voltage (BV)- RON,sp figure of merit approach the ideal Baligas power law, in addition, breaks the quasi-saturation limitation with enhanced device safe operating area (SOA). The optimal charge balance and geometrical design to achieve the lowest specific ON resistance (RON,sp) with the desired maximum high BV are displayed and discussed by simulations and experimental results. The 2-D simulations confirmed that, compared with conventional triple-RESURF structures, the presented device provides a fourfold reduction in the surface electric field on the source side and a 32% improvement in blocking voltage. The specific ON resistance demonstrates superior 40% lower performance than published Junction Isolation LDMOS device families. In addition, its twofold increase in SOA extension can improve the performance of circuit designs for switching power supply applications.

p

Lateral insulated gate bipolar transistors (IGBTs) in 4H-SiC are demonstrated for the first time. The devices were fabricated based on three different designs to investigate the effects of buffer doping and carrier lifetime on device performance. Experimental results show that, with a lightly doped buffer, a short drift region length, and an improved carrier lifetime, the common base current gain of the parasitic bipolar junction transistor (BJT) is improved, leading to a higher current capability of the IGBT. The differential on-resistance of the lateral IGBT with Ld = 20 μm is smaller than that of a lateral MOSFET counterpart, implying partial conductivity modulation in the drift region.

-GaN With Post Metallization Annealing and

This paper presents, for the first time, the study of the application of a lateral diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) in a common-gate configuration to radio-frequency (RF) transmit/receive (T/R) switching circuits. A single-pole double-throw (SPDT) 900-MHz T/R switch is implemented using 0.25-LDMOSFET foundry technology. Measured results show that our switching circuit can achieve a low insertion loss of 0.82 dB and a high power handling capability of 27 dBm. This result is promising in integrating power management integrated circuits, RF power amplifiers, and switching circuits in a single chip, based on LDMOSFET technology, to realize an RF transmit front-end system-on-chip solution.

(\hbox{NH}_{4})_{2}\hbox{S}_{X}

In this paper, an observation of drain current instability on p-GaN gate AlGaN/GaN HEMTs is reported. Contrary to the Schottky gate AlGaN/GaN HEMTs, which show stable and consistent Id-Vd curves under different pulsed conditions, the Id-Vd curves for p-GaN gate AlGaN/GaN HEMTs show a dispersion in the saturation region under the same pulse conditions, which cannot be explained by the trapping of electrons in the material. A model considering the trapping of holes in the p-GaN gate under different gate and drain biases is proposed to explain this new phenomenon.

Treatments

Design and fabrication of 4H-SiC lateral high-voltage devices on semi-insulating substrates based on the charge compensation principle have been investigated in this work. In the simulation, field plates are critical in relieving the electric field crowding at junction corners at high reverse biases. By incorporating field plates with proper lengths, the breakdown voltage (BV) of a single-zone reduced-surface-field (RESURF) device with a 100- μm drift region can be improved from 3360 to 5880 V. The BV can be further enhanced to 8000 V by using a two-zone RESURF structure. The reduction in BV by 10% charge imbalance variation is also improved from 49% for a single-zone structure to 36% for a two-zone structure. Simulation also shows that oxide charges and other surface charges will offset the optimized charge imbalance conditions and, therefore, should be considered in design if the amount is significant. A 4H-SiC JFET with a two-zone RESURF region was fabricated to demonstrate the advantages of lateral devices based on these concepts. The fabricated lateral 4H-SiC JFET has a BV of 4200 V and a specific on -resistance of 454 mΩ·cm2. The figure of merit is as high as 38.8 MW/cm2.

Modelling temperature dependence on AlGaN/GaN power HEMT device characteristics

High-voltage 4H-SiC lateral MOSFETs with different gate layouts, channel lengths, and drift region lengths were fabricated on the (0001) face of a high-purity semi-insulating substrate. A breakdown voltage of 3520 V was achieved on a circular gate device with a channel length of 5 μm and a drift region length of 80 μm. This is, to the best knowledge of the authors, the highest value among 4H-SiC lateral MOSFETs ever reported. The specific on-resistance is 600 mΩ-cm2, which results in a figure-of-merit (BV2/Ronsp) of 20.6 MW/cm2, which is comparable with other 4H-SiC lateral MOSFETs reported in the literature. It was found that the use of a circular gate layout effectively reduces the reverse leakage current at high voltages.