Ko-Tao Lee

A Four-FET Method for Extracting Mobility in FETs Without Field Oxide

Many fabricated III-V MOSFETs have electrically thin field oxide (FOX) that leads to parasitic currents and parasitic capacitances. When extracting long-channel mobility of such devices using the conventional two-FET method, some of these parasitic components are not subtracted out. In this paper, we present a simple four-FET method for extracting long-channel mobility that works well even when the equivalent oxide thickness (EOT) of the FOX is equal to the EOT of the FET gate oxide.

Electron mobility in thin In 0.53 Ga 0.47 As channel

Channel thickness Tch dependence of electron mobility μκρρ in thin In<inf>0.53</inf>Ga<inf>0.47</inf>As channels was investigated at temperatures T from 35 to 300 K using conventional parametric and pulsed I<inf>D</inf>-measurements, including a novel technique with time resolution down to 10 ns. It is show that accurate mobility measurements can be obtained using low T and/or fast pulsed measurements, thus avoiding significant underestimations of μκρρ due to charge trapping with slow/parametric measurements. Furthermore, annealing is demonstrated to strongly suppress charge trapping, which results in μ<inf>κρρ</inf> = 1015 cm²/Vs at T<inf>ch</inf> = 7.1 nm, carrier density Ns = 3 × 10¹² cm⁻², and T = 300 K. We demonstrate that room-temperature μκρρ degrades by less than 10% as T<inf>ch</inf> is scaled from 300 nm down to 7 nm, thus indicating that there is no “mobility bottleneck” down to T<inf>ch</inf> = 7 nm.

High-performance CMOS-compatible self-aligned In 0.53 Ga 0.47 As MOSFETs with GMSAT over 2200 µS/µm at V DD = 0.5 V

We demonstrate high-performance self-aligned In_0.53Ga_0.47As-channel MOSFETs with effective channel length L_EFF down to 20 nm, peak transconductance G_MSAT over 2200 μS/μm at L_EFF = 30 nm and supply voltage V_DD = 0.5 V, thin inversion oxide thickness T_INV = 1.8 nm, and low series resistance R_EXT = 270 Ω.μm. These MOSFETs operate within 20% of the ballistic limit for L_EFF ≤ 30 nm and are among the best In_0.53Ga_0.47As FETs in literature. We investigate the effects of channel/barrier doping on FET performance and show that increase in mobility beyond ~ 500 cm²/Vs has progressively smaller impact as L_EFF is scaled down. Our self-aligned MOSFETs were fabricated using a CMOS-compatible process flow that includes gate and spacer formation using RIE, source/drain extension (SDE) implantation, and in-situ-doped raised source/drain (RSD) epitaxy. This process flow is manufacturable and easily extendable to non-planar architectures.