Chih-Hong Hwang

Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies

This paper, for the first time, estimates the influences of the intrinsic-parameter fluctuations consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and random-dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold-voltage fluctuation (¿V th) ; however, the WKF brings less impact on the gate capacitance and the cutoff frequency due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the ¿V th and is therefore proportional to the trend of ¿V th. The power fluctuation consisting of the dynamic, short-circuit, and static powers is further investigated. The total power fluctuation for the planar MOSFET circuits is 15.2%, which is substantial in the reliability of circuits and systems. The static power is a minor part of the total power; however, its fluctuation is significant because of the serious fluctuation of the leakage current. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3-dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuit characteristic fluctuations due to the significant gate-capacitance fluctuations, and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can, in turn, be used to optimize nanoscale MOSFETs and circuits.

Discrete-dopant-induced characteristic fluctuations in 16nm multiple-gate silicon-on-insulator devices

The impact of the number and position of discrete dopants on device characteristics is crucial in determining the behavior of nanoscale semiconductor devices. This study explores discrete-dopant-induced characteristic fluctuations in 16nm single-, double-, triple-, and (square shape) surrounding-gate silicon-on-insulator (SOI) devices. Discrete dopants are statistically positioned in the three-dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing “dopant concentration variation” and “dopant position fluctuation.” An experimentally validated simulation was conducted to investigate the threshold voltage (Vth) fluctuation and the variation of the on- and off-state currents of the four explored structures. The fluctuations of Vth of the double-, triple- and surrounding-gate devices are 2.2, 3.3 and 4 times smaller, respectively, than that of planar SOI. Results of this study provide further insight into the problem of fluctuation and the mechanism of i...

Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits

The impact of the number and position of discrete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to investigate the discrete-dopant-induced timing-characteristic fluctuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations of NAND and NOR circuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation of NAND and NOR are expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function- and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale MOS field-effect-transistor circuits.

High-Frequency Characteristic Fluctuations of Nano-MOSFET Circuit Induced by Random Dopants

As the dimension of semiconductor device shrunk into nanometer scale (nanoscale), characteristic fluctuation is more pronounced, and become crucial for circuit design. In this paper, discrete-dopant-induced characteristic fluctuation of 16-nm-gate metal-oxide-semiconductor field effect transistors (MOSFET) circuit under high-frequency regime is quantitatively studied. The circuit gain, the 3 dB bandwidth and the unity-gain bandwidth of the tested nanoscale transistor circuit are calculated concurrently capturing the discrete-dopant-number- and discrete- dopant-position-induced fluctuations in the large-scale statistically sound ldquoatomisticrdquo device/circuit coupled simulation. For the 16-nm-gate MOSFET circuit, the number of discrete dopants, varying from zero to 14, may result in 5.7% variation of the circuit gain, 14.1% variation of the 3 dB bandwidth, and 10.4% variation of the unity-gain bandwidth. To suppress the high-frequency characteristic fluctuations, an improved doping distribution along the longitudinal diffusion direction from the MOSFETs surface to substrate is further performed to examine the associated fluctuation. The improved vertical doping profile with less dopants locating near surface of channel effectively reduces the fluctuations of the circuit gain, the 3 dB bandwidth and the unity-gain bandwidth dramatically. Compared with the original doping profile, the reduction is 32.3%, 19.4% and 51.8%, respectively. This study provides an insight into random-dopant-induced intrinsic high-frequency characteristic fluctuations and verifies the potential fluctuation suppression technique on high-frequency characteristic fluctuations of nanoscale transistor circuit.

Effect of Fin Angle on Electrical Characteristics of Nanoscale Round-Top-Gate Bulk FinFETs

In this brief, electrical characteristics of 25-nm round-top-gate fin-typed field-effect transistors (FinFETs) on silicon wafers are numerically explored. With an ideal fin angle (i.e., thetas = 90deg), the FinFETs with doped and undoped (for this case, the device has a metal gate) channels that was fabricated on silicon and silicon-on-insulator wafers are simulated and compared. With a 3-D quantum-correction-transport simulation, characteristic comparison shows that bulk FinFETs with the undoped channel possess promising electrical characteristics. By considering different short-channel effects, dependence of the device performance on the nonideal fin angle and fin height is further investigated. Optimal structure configuration for the round-top-gate bulk FinFETs is thus drawn to show the strategy of fabrication in sub-25-nm MOSFET devices.

The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding- gate field-effect transistor and circuit

The silicon (Si) surrounding-gate metal-oxide-semiconductor field-effect transistor (MOSFET) has ultimate gate structures and is a potential candidate for use in next-generation high-performance nano-devices. However, because of limitations of the fabrication process, theoretically ideally round shape of the surrounding gate may not always guarantee. These limitations may lead to the formation of an ellipse-shaped surrounding gate with major (a) and minor (b) axes of different lengths. In this study, the effect of the geometry aspect ratio, a/b, on the dc and ac characteristics of the 16 nm gate ellipse-shaped surrounding-gate MOSFETs and circuits is examined by using a three-dimensional coupled device-circuit simulation technique. The dependences of electrical characteristics on the geometry aspect ratio are evaluated with reference to various device characteristics and the circuit properties, including the circuit gain, the 3 dB bandwidth, the unity-gain bandwidth, the rise/fall time and the delay time. In analog circuits, the device with an aspect ratio of less than 1 is promising because the short-channel effect is suppressed. However, for a digital circuit configuration, the transient response of the circuit relies on the charge/discharge capability of the transistor. Thus, a device with a large aspect ratio, such as 2, will be more suitable for digital applications.

Simulation of characteristic variation in 16 nm gate FinFET devices due to intrinsic parameter fluctuations

High-kappa/metal-gate and vertical channel transistors are well-known solutions to continue the device scaling. This work extensively explores the physics and mechanism of the intrinsic parameter fluctuations in nanoscale fin-type field-effect transistors by using an experimentally validated three-dimensional quantum-corrected device simulation. The dominance fluctuation sources in threshold voltage, gate capacitance and cutoff frequency have been found. The emerging fluctuation source, workfunction fluctuation, shows significant impacts on DC characteristics; however, its impact is reduced in AC characteristics due to the screening effect of the inversion layer. Additionally, the channel discrete dopant may enhance the electric field and therefore make the averaged cutoff frequency of fluctuated devices larger than the nominal value of cutoff frequency.

Discrete-Dopant-Induced Timing Fluctuation and Suppression in Nanoscale CMOS Circuit

As the dimensions of semiconductor devices continue to be reduced, device fluctuations have become critical to determining the accuracy of timing in circuits and systems. This brief studies the discrete-dopant-induced timing characteristic fluctuations in 16-nm-gate complementary metal-oxide-semiconductor (CMOS) circuits using a 3-D ldquoatomisticrdquo coupled device-circuit simulation. The accuracy of the simulation has been confirmed by using the experimentally calibrated transistor physical model. For a 16-nm-gate CMOS inverter, 3.5%, 2.4%, 18.3%, and 13.2% normalized fluctuations in the rise time, fall time, high-to-low delay time, and low-to-high delay time, respectively, are found. Random dopants may cause significant timing fluctuations in the studied circuits. Suppression approaches that are based on the circuit and device design viewpoints are implemented to examine the associated characteristic fluctuations. The use of shunted transistors in the circuit provides similar suppression to the use of a device with doubled width. However, both approaches increase the chip area. To eliminate the need to increase the chip area, channel engineering approaches (vertical and lateral) are proposed, and their effectiveness in reducing the timing fluctuation is demonstrated.

Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuits

Modeling of device variability is crucial for the accuracy of timing in circuits and systems, and the stability of high-frequency application. Unfortunately, due to the randomness of dopant position in device, the fluctuation of device gate capacitance is nonlinear and hard to be modeled in current compact models. Therefore, a large-scale statistically sound ldquoatomisticrdquo device/circuit coupled simulation approach is proposed to characterize the random-dopant-induced characteristic fluctuations in 16-nm-gate CMOS integrated circuits concurrently capturing the discrete-dopant-number- and discrete-dopant-position-induced fluctuations. The variations of transition time of digital circuit (inverter, NAND, and NOR gates) and high-frequency characteristic of common-source amplifier are estimated. For the digital circuits, the function-dependent and circuit-topology-dependent characteristic fluctuations resulted from random nature of discrete dopants is for the first time discussed. This study provides an insight into random-dopant- induced intrinsic timing and high-frequency characteristic fluctuations. The accuracy of the simulation technique is confirmed by the use of experimentally calibrated transistor physical model.

DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit

Silicon-based nanowire field effect transistors (FETs) are potentially next-generation candidates for achieving high-performance targets of the International Roadmap for Semiconductors due to their superior reduction of the short-channel effects and excellent compatibility with planar complementary metal oxide semiconductor (CMOS) fabrication process. In this work, we for the first time numerically explore the dc baseband and high-frequency characteristics, and the design of the device aspect ratio (channel length/channel thickness) for the silicon nanowire FET circuits by using a three-dimensional device/circuit-coupled mixed-mode simulation technique. With the experimentally validated simulation approach, the result shows the rather prolific dc baseband and high-frequency properties of silicon-based nanowire FET devices as active components. In design of silicon nanowire FETs, taking the nanowires radius and channel length as two crucial factors, the demands of the device aspect ratio on dc characteristics are found to be inversely proportional to the demands of the high-frequency characteristics. Therefore, to compromise both the dc and high-frequency characteristics, the design margin of the device aspect ratio restricted, in which the requirements of dc and high-frequency characteristics provide aspect ratio upper and lower bounds, respectively. Moreover, the design margin will be more tightened for a device with larger radius due to the weakened channel controllability. The extensive results and analyses are presented for the promising devices for the design of high-frequency analog applications.