Ming-Hung Han

Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies

This paper, for the first time, estimates the influences of the intrinsic-parameter fluctuations consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and random-dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold-voltage fluctuation (¿V th) ; however, the WKF brings less impact on the gate capacitance and the cutoff frequency due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the ¿V th and is therefore proportional to the trend of ¿V th. The power fluctuation consisting of the dynamic, short-circuit, and static powers is further investigated. The total power fluctuation for the planar MOSFET circuits is 15.2%, which is substantial in the reliability of circuits and systems. The static power is a minor part of the total power; however, its fluctuation is significant because of the serious fluctuation of the leakage current. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3-dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuit characteristic fluctuations due to the significant gate-capacitance fluctuations, and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can, in turn, be used to optimize nanoscale MOSFETs and circuits.

3D 65nm CMOS with 320°C microwave dopant activation

For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.

Device and Circuit Performance Estimation of Junctionless Bulk FinFETs

The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (<i>V</i>_th) roll-off characteristics at supply voltage (<i>V</i>_DD) 1 V. Analyses of electron density and electricfield distributions in on-state and off-state also show that the JL devices have better on-off current ratios. Regarding design aspects, the effects of channel doping concentration (<i>N</i>_ch) and Fin height (<i>H</i>)/width (<i>W</i>) on device <i>V</i>_th are also compared. In addition, the <i>V</i>_th of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (<i>N</i>_sub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (<i>t</i>_HL) and low-to-high delay time (<i>t</i>_LH) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.

3D device simulation of work function and interface trap fluctuations on high-κ / metal gate devices

This work, for the first time, examines the work function fluctuation (WKF) and interface trap fluctuation (ITF) using experimentally calibrated 3D device simulation on high-κ / metal gate technology. The random WKs result in 36.7 mV threshold voltage fluctuation (σVth) for 16 nm N-MOSFETs with TiN gate, which is rather different from the result of averaged WKF (AWKF) method [1] due to localized random WK effect. The ITF affects the subthreshold region (the normalized σID > 48%) and is suppressed for devices under strong inversion. Estimation of statistical covariance confirms the dependence of IT on the metal gates WK; thus, the impacts of WKF and ITF on device and circuit variability should be considered together properly. Such variability induced static noise margin fluctuation of SRAM exceeds the influence of random dopants and cannot be ignored.

Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel

This letter demonstrates for the first time junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm). The subthreshold swing is 61 mV/decade and the ON/OFF current ratio is close to 108 because of the excellent gate controllability and ultrathin channel. The JL-GAA TFTs have a low drain-induced barrier lowering value of 6 mV/V, indicating greater suppression of the short-channel effect than in JL-planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future system-on-panel and system-on-chip applications.

Simulation of characteristic variation in 16 nm gate FinFET devices due to intrinsic parameter fluctuations

High-kappa/metal-gate and vertical channel transistors are well-known solutions to continue the device scaling. This work extensively explores the physics and mechanism of the intrinsic parameter fluctuations in nanoscale fin-type field-effect transistors by using an experimentally validated three-dimensional quantum-corrected device simulation. The dominance fluctuation sources in threshold voltage, gate capacitance and cutoff frequency have been found. The emerging fluctuation source, workfunction fluctuation, shows significant impacts on DC characteristics; however, its impact is reduced in AC characteristics due to the screening effect of the inversion layer. Additionally, the channel discrete dopant may enhance the electric field and therefore make the averaged cutoff frequency of fluctuated devices larger than the nominal value of cutoff frequency.

Statistical Simulation of Static Noise Margin Variability in Static Random Access Memory

In this paper, we examine the impact of random-dopant-fluctuation (RDF), process-variation-effect (PVE), and workfunction-fluctuation (WKF), on 16-nm-gate metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) cells. For planar MOSFETs with a threshold voltage of 140 mV, the nominal static noise margin (SNM) of six-transistor (6T)-SRAM with unitary cell ratio (CR) is only 20 mV; and the normalized SNM fluctuations (SNM) induced by RDF, PVE, and WKF are 80%, 31%, and 48%, respectively, which may damage SRAMs operation. Two improvement approaches are further implemented; first, eight-transistor (8T)-SRAM and 6T-SRAM with increased CR are examined. Compared with the conventional 6T-SRAM, under the same , the SNM of 8T-SRAM is enlarged to 233 mV and the corresponding RDF, PVE, and WKF-induced SNM are reduced to 9.5%, 6.4%, and 7%, respectively, at a cost of 30% extra chip area. Without increasing chip area, device with raised , doping profile engineering and using silicon-on-insulator fin-type field-effect transistors (SOI FinFETs) are further advanced. The 6T SOI FinFETs SRAM exhibits the smallest , with merely 5.3%, 1.2%, and 2.3%, resulting from RDF, PVE, and WKF, respectively, where the value of SNM is equal to 125 mV.

High voltage characteristics of junctionless poly-silicon thin film transistors

The breakdown voltage (VBD) and breakdown mechanism of junctionless (JL) poly-Si thin film transistor (TFT) were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum-corrected hydrodynamic transport device simulation. The simulated results are correspondent with experimental ones. The analyses of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain. The JL TFT shows excellent breakdown characteristics; the off-state VBD of 53.4 V is several times larger than VBD of 9.5 V in IM TFT with same device size. JL devices have large potential for high voltage power metal-oxide-semiconductor devices and circuit applications.

Statistical Analysis of Metal Gate Workfunction Variability, Process Variation, and Random Dopant Fluctuation in Nano-CMOS Circuits

This work for the first time estimates the influences of the intrinsic parameter fluctuations consisting of metal gate workfunction fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold voltage fluctuation; however, the WKF brings less impact on the gate capacitance due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the threshold voltage fluctuation, and therefore is proportional to the trend of threshold voltage fluctuation. For an amplifier circuit, the high- frequency characteristics, the circuit gain, the 3dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency, are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuits characteristic fluctuations due to the significant gate capacitance fluctuations and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can in turn be used to optimize nanoscale MOSFET and circuits.

Improving Breakdown Voltage of LDMOS Using a Novel Cost Effective Design

A reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device with the concept of charge compensation using p-implant layer (PIL) without additional process step is proposed in standard 0.18-μm technology. By simply using the p-type drift drain (PDD) implantation of p-type LDMOS into n-type LDMOS, breakdown voltage (VBD) is substantially improved. For a thorough study of device phenomena, hydrodynamic transport simulations are first performed to analyze the electric field distributions at high voltage bias in order to explain increases in breakdown voltage and predict its optimal design parameter. Then fabrication of the devices is performed and shows that the breakdown voltages increase significantly. The measurement results show a 12% improvement in VBD and a 5% improvement in figure of merit (FOM). Throughout the fabrication process, the enlarged breakdown voltage obtained by the PIL without additional process and device area show the potential of cost effective. Because such devices have good off-state breakdown voltage and specific on-resistance, they are very competitive with similar technologies and promising system-on-chip (SOC) applications.