Chih-Lin Chen

Self-Sampled All-MOS ASK Demodulator for Lower ISM Band Applications

An all-MOS ASK demodulator with a wide bandwidth for lower industrial, scientific and medical (ISM) band applications is presented. The chip area is reduced without using any passive element. It is very compact to be integrated in a system-on-chip for wireless biomedical applications, particularly in biomedical implants. Because of low area cost and low power consumption, the proposed design is also easy to integrate in other mobile medical devices. The self-sampled loop with a MOS equivalent capacitor compensation mechanism enlarges the bandwidth, which is more than enough to be adopted in any application using lower ISM bands.

A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit

This paper proposes a high speed bidirectional mixed-voltage I/O buffer using 90 nm 1.2 V standard CMOS process. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit/receive 2 × VDD voltage level signal without any gate-oxide overstress hazard. Most important of all, the gate-oxide overstress hazard is eliminated by adopting a dual-path gate-tracking circuit. The maximum data rate and jitter are measured to be 800 Mbps/12.37 ps and 704 Mbps/14.79 ps for 1.2 V and 2.5 V signal voltage, respectively, with a given capacitive load of 20 pF.

A high voltage analog multiplexer with digital calibration for battery management systems

This work presents a multi-channel high voltage analog multiplexer with digital calibration for battery management systems (BMS). For a high voltage battery management systems, the front end circuit must be able to accommodate input voltage up to tens of volts, perhaps even hundreds of volts. To realize a possible solution on silicon, the front end of BMS shall be fabricated using an advanced HV (high voltage) semiconductor process, which usually is constrained by the voltage limitation between gate and source of HV devices. To overcome such a limitation, a high voltage gate control circuit is proposed in this work, including digital calibration that can compensate the output voltage loss of the multiplexer. An experimental prototype is implemented using a typical 0.25 μm 1-poly 3-metal 60V BCD process. The post-layout-extracted simulation results reveal that the worst-case error is less than 2 mV with calibration, which is 91% improvement compared with the state of art based on thorough simulations.

A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems

This paper presents a voltage monitoring IC with high-voltage multiplexer (HVMUX) and HV transceiver for battery interconnect module (BIM) used in battery management systems (BMSs). The voltage monitoring IC must be able to accommodate input voltage up to tens of volts, perhaps even hundreds of volts, which is difficult to be realized using a logic-based solution. To realize a solution on silicon, the voltage monitoring IC shall be fabricated using an advanced HV semiconductor process, which usually is constrained by the voltage drop limitation between gate and source of HV devices. To overcome such a limitation, an HV switch is proposed in this paper, including an HV gate voltage driver (HVGVD) driving the HV MOS without any over-voltage hazard. In addition, an HV transceiver is proposed using CMOS transistors without any isolator. An experimental prototype is fabricated using a typical 0.25 μm 1-poly 3-metal 60 V BCD process. The measurement results reveal that the error and off-isolation of HVMUX is less than 2.54% and -92 dB@1 MHz, respectively. Meanwhile, the HV transceiver can transmit and receive data with a -32 ~ +32 V common voltage.

A slew rate self-adjusting 2×VDD output buffer With PVT compensation

A novel PVT (Process, Voltage, Temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, voltage, and temperature deviation could be detected, respectively. The proposed design is implemented using a typical 90 nm CMOS process to justify the performance. By adjusting output currents, the slew rate of output signal could be compensated over 38% and the maximum data rate with compensation is 345 MHz.

A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems

In this paper, a 60 V tolerance transceiver with ESD (electrostatic discharge) protection is proposed for FlexRay-based communication systems. The FlexRay transceiver comprises three protective devices, including an over-voltage detector, high-voltage ESD devices, and high-voltage diodes. The over-voltage detector is in charge of detecting bus (BP and BM) status to distinguish whether any hazard has happened. If the over-voltage detector is activated, the FlexRay transceiver must be turned off for safety. The high-voltage ESD device uses a base-floating PNP serving as a bi-directional device. Besides, it can protect the FlexRay transceiver whenever it is short-circuited in positive or negative high voltages. Notably, the high-voltage diode will eliminate the negative leakage current when negative high voltage hazards appear in FlexRay channels. An experimental prototype is implemented using a 0.18 μm CMOS mixed-signal based generation II HV BCD process. The measurement results justify the functional correctness and 60 V tolerance of the proposed FlexRay transceiver design.

On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers

A novel PVT (Process, Voltage, Temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, voltage, and temperature deviation could be detected, respectively. The proposed design is implemented using a typical 90 nm CMOS process to justify the performance. By adjusting output currents, the slew rate of output signal could be compensated over 26% and the maximum data rate is 330 MHz.

A delay-based transceiver with over-current protection for ECU nodes in automobile FlexRay systems

This work presents a FlexRay Transceiver (FRT) used in an in-vehicle network compliant with the latest FlexRay physical layer standards. The proposed FRT utilizes a delay-based mechanism to reduce glitches. Besides, an Over-current Protection (OCP) circuit is included to avoid short-circuit hazard. The proposed is implemented on silicon using a typical 0.18 μm CMOS process. The total core area is 0.774 × 0.565 mm2 and the power consumption is 158.4 mW at 10 Mbps data rate.

A 2íVDD output buffer with PVT detector for slew rate compensation

A novel PVT (process, voltage, temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2xVDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, supply voltage, and temperature (PVT) is detected, respectively. Based on the detected PVT corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the slew rate of the output can be adjusted as well. The proposed design is implemented using a typical 90nm CMOS process to justify the slew rate performance. By the on-silicon measurements, the slew rate of output signal is compensated over 26%, the maximum slew rate is 1.65 (V/ns), the maximum data rate is 330MHz given 1.2/0.9V supply voltage with a 20pF load, the core area of the proposed design is 0.056x0.406mm^2, and the power consumption is 2.2mW at 330MHz data rate.

A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits

This work presents a phase-locked loop (PLL)-based clock and data recovery (CDR) circuit with a lock detector loop to reduce the voltage ripple of voltage-controlled oscillator (VCO). A tunable charge pump is used in this work to adjust the charge current depending on the state of lock detector loop, which is determined by seven clocks with equal phase difference. An experimental prototype is implemented using a typical 0.18-