Ron-Chi Kuo

Self-Sampled All-MOS ASK Demodulator for Lower ISM Band Applications

An all-MOS ASK demodulator with a wide bandwidth for lower industrial, scientific and medical (ISM) band applications is presented. The chip area is reduced without using any passive element. It is very compact to be integrated in a system-on-chip for wireless biomedical applications, particularly in biomedical implants. Because of low area cost and low power consumption, the proposed design is also easy to integrate in other mobile medical devices. The self-sampled loop with a MOS equivalent capacitor compensation mechanism enlarges the bandwidth, which is more than enough to be adopted in any application using lower ISM bands.

0.9 V to 5 V Bidirectional Mixed-Voltage I/O Buffer With an ESD Protection Output Stage

A 0.9 V to 5 V (0.9/1.2/1.8/2.5/3.3/5 V) mixed-voltage I/O buffer with NMOS clamping technique is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit a sub-3 × VDD voltage-level signal without gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a floating N-well circuit. The maximum data rate is measured at 66 MHz for 5/3.3/2.5/1.8/1.2/0.9 V with an equivalent probe capacitive load of 10 pF.

On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2

A novel process and temperature compensation design for 2 VDD output buffers is proposed, where the threshold voltages (Vth) of PMOSs and NMOSs varying with process and temperature deviation could be detected, respectively. A prototype 2 × VDD output buffer using the proposed compensation design is fabricated using a typical 0.18 μm CMOS process. By adjusting output currents, the slew rate of output signals could be compensated over 117%. The maximum data rate with compensation is 120 MHz in contrast with 95 MHz without compensation, which is measured on silicon with an equivalent probe capacitive load of 10 pF.

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A novel PVT (Process, Voltage, Temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, voltage, and temperature deviation could be detected, respectively. The proposed design is implemented using a typical 90 nm CMOS process to justify the performance. By adjusting output currents, the slew rate of output signal could be compensated over 38% and the maximum data rate with compensation is 345 MHz.

VDD Output Buffers

A novel PVT (Process, Voltage, Temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, voltage, and temperature deviation could be detected, respectively. The proposed design is implemented using a typical 90 nm CMOS process to justify the performance. By adjusting output currents, the slew rate of output signal could be compensated over 26% and the maximum data rate is 330 MHz.

A slew rate self-adjusting 2×VDD output buffer With PVT compensation

A novel PVT (process, voltage, temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2xVDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, supply voltage, and temperature (PVT) is detected, respectively. Based on the detected PVT corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the slew rate of the output can be adjusted as well. The proposed design is implemented using a typical 90nm CMOS process to justify the slew rate performance. By the on-silicon measurements, the slew rate of output signal is compensated over 26%, the maximum slew rate is 1.65 (V/ns), the maximum data rate is 330MHz given 1.2/0.9V supply voltage with a 20pF load, the core area of the proposed design is 0.056x0.406mm^2, and the power consumption is 2.2mW at 330MHz data rate.

On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers

A 1.0 V to 1.8 V mixed-voltage I/O buffer implemented with 90-nm 1-V standard CMOS devices is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 2×VDD voltage level signal without any gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to be 340 MHz and 450 MHz for 1.8 V and 1.0 V, respectively, with a given capacitive load of 20 pF.

A 2íVDD output buffer with PVT detector for slew rate compensation

A high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an Error Amplifier, the independence of off-chip capacitor and ESR is ensured for different load currents and operating voltages. Therefore, in low Iddq or low voltage scenarios, the total error of the output voltage caused by line and load variations is less than ±3% according to on-silicon measurement results.

450 MHz 1.0 V to 1.8 V bidirectional mixed-voltage I/O buffer using 90-nm process

A PCI166-compatible 3×VDD mixed-voltage I/O buffer with ESD protection consideration is proposed. By using a compact Dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit sub-3×VDD voltage level signal without gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a Floating N-well circuit. The maximum data rate is simulated to be 166/166/166/100/80 MHz when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, respectively, with an equivalent probe capacitive load of 10 pF.

A high precision low dropout regulator with nested feedback loops

A 0.9 V to 5 V (0.9/1.2/1.8/2.5/3.5/5 V) mixed-voltage I/O buffer with NMOS clamping technique is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 3×VDD voltage level signal without gate-oxide overstress hazard. Besides, the leakage current effect is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to 140/120/120/120/80/40 Mbps for 5/3.3/2.5/1.8/1.2/0.9 V, respectively, with a given capacitive load of 10 pF.