Chih-Sheng Chang

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (µ-bump) processes and joining, that form the building blocks for 3D IC technology were developed based on established Si foundry technologies. Test vehicles (TVs) have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme.

Leakage scaling in deep submicron CMOS for SoC

In this paper, we demonstrate the effects of CMOS technology scaling on the high temperature characteristics (from 25/spl deg/C to 125/spl deg/C) of the four components of off-state drain leakage (I/sub off/) (i.e. subthreshold leakage (I/sub sub/), gate edge-direct-tunneling leakage (I/sub EDT/), gate-induced drain-leakage (I/sub GIDL/), and bulk band-to-band-tunneling leakage (I/sub B-BTBT/)). In addition, the high temperature characteristics of I/sub off/ with reverse body bias (V/sub B/) for the further reduction of the standby leakage are also demonstrated. The discussion is based on the data measured from three CMOS logic technologies (i.e., low-voltage and high performance (LV), low-power (LP), and ultra-low-power (ULP)) and three generations (0.18 /spl mu/m, 0.15 /spl mu/m, and 0.13 /spl mu/m). Experiments show that the optimum V/sub B/, which minimizes I/sub off/, is a function of temperature. The experiments also show that for CMOS logic technologies of the next generations, it is important to control I/sub B-BTBT/ and I/sub GIDL/ by reducing effective doping concentration and doping gradient. It seems that in order to conform on-state gate leakage (I/sub G-on/) and I/sub EDT/ specifications and to retain a 10-20% performance improvement at the same time, it is indispensable to use high-quality and high-dielectric-constant materials to reduce effective oxide thickness (EOT). The role of each leakage component in SRAM standby current (I/sub SB/) is also analyzed.

Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs

The effect of shallow trench isolation mechanical stress on MOSFET dopant diffusion has become significant, and affects device behavior for sub-100-nm technologies. This paper presents a stress-dependent dopant diffusion model and demonstrates its capability to reflect experimental results for a state-of-the-art logic CMOS technology. The proposed stress-dependent dopant diffusion model is shown to successfully reproduce device characteristics covering a wide range of active area sizes, gate lengths, and device operating conditions.

Interface induced uphill diffusion of boron: an effective approach for ultrashallow junction

This paper investigates anomalous diffusion behavior for ultra low energy implants in the extension or tip of PMOS devices. Transient enhanced diffusion (TED) is minimal at these low energies, since excess interstitials are very close to the surface. Instead, interface induced uphill diffusion is found, for the first time, to dominate during low temperature thermal cycles. The interface pile-up dynamics can be taken advantage of to produce shallower junctions and improve short channel effect control in PMOS devices. Attempts to minimize TED before spacer deposition by inclusion of extra RTA anneals are shown to be detrimental to forming boron ultra shallow junctions.

Temperature dependent channel backscattering coefficients in nanoscale MOSFETs

The ratio of the mean-free-path to the critical length near the low-field source is key to channel backscattering characteristics in nanoFETs. To extract it, we perform temperature experiment from -40/spl deg/C to 75/spl deg/C on 17 /spl Aring/ thick gate oxide MOSFETs with varying mask gate lengths down to 75 nm. In this paper we report that once the saturation drain current is measured against temperature, the mean-free-path /spl lambda/ with respect to the critical length l can readily be assessed at specific temperature. Dependencies on gate length, drain voltage, and gate voltage are then established that further enable nanoFETs scaling projections. The temperature dependent version of existing backscattering model is derived in this work.

Transistor-and Circuit-Design Optimization for Low-Power CMOS

CMOS-technology scaling has moved to a power-constrained condition regardless of the application segments. Power management in advanced CMOS technology drives the need to conciliate scaling-driven fundamental material limitations with product and application evolution requirements. Flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize systems on a chip. This paper reviews issues associated with transistor scaling and co-optimization for power-management circuit-design schemes for active-and leakage-power control. This paper also addresses the derived trends and implications on I/O and analog-transistor scaling.

A 7nm CMOS platform technology featuring 4 th generation FinFET transistors with a 0.027um 2 high density 6-T SRAM cell for mobile SoC applications

For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This technology provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V. The 4th generation FinFET transistors are optimized with device mismatch reduction by 25%∼35% and multi-Vt device options to enable low power and high performance design requirements.

Orthotropic stress field induced by TSV and its impact on device performance

An orthotropic stress field was observed in the vicinity of the Cu-filled TSV on nominal (100) silicon substrate from both μRaman measured data and validated FEM result. The orthotropic elastic behavior of silicon in the (100) plane is believed to be the reason. The FEM model was further validated by the comparison with the measured electrical data, and used to predict the device performance shift under the influence of the TSV-induced stress. The performance shift pattern also showed an orthotropic pattern. This finding has profound implication on 3D silicon stacking design rule and system integration.

A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration

A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (V_cc) of 1.8V, and a leakage current (I_LK) below 1 fA/μm² under +/-2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/μm², respectively, with their corresponding I_LK below 0.48, 0.19 and 0.09 fAmp/μm². Process reliability related defect density (D₀) of the interposer HK-MiM is as low as 0.095% cm^-2 as judged by a 10 years lifetime breakdown voltage (V_bd) criterion at V_cc=3.2V. This low D₀ ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm² within the Si interposer. Moreover, the V_bd tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., I_LK & V_bd tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.

Demonstration of a sub-0.03 um 2 high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node

For the first time, we demonstrate the smallest, fully functional 32Mb 6-T high density SRAM reported in literature with scaled bulk FinFETs for CMOS technology beyond 10nm node. Scaled FinFET devices exhibit excellent electrostatic with DIBL of <;45mV/V and sub-threshold swing of <;65mV/decade and competitive drive current. Static noise margin of ~90mV for the high density SRAM operated down to 0.45V is achieved.