S.P. Jeng

High-aspect ratio through silicon via (TSV) technology

The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm × 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm × 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.

Thinning, stacking, and TSV proximity effects for Poly and High-K/Metal Gate CMOS devices in an advanced 3D integration process

An advanced 3D integration process featuring through silicon via (TSV) and chip-on-wafer (CoW) technologies has been demonstrated. Using this 3D process, Poly and High-K/Metal Gate (HKMG) CMOS wafers have been successfully thinned and stacked, showing little to no degradation in the process. The effect of TSV induced mechanical stress on ΔIdsat for HKMG is found to be smaller as compared to Poly Gate devices for the same channel length (ΔIdsat ratio of HKMG to Poly is ~0.3 and ~0.5 for PMOS and NMOS, respectively). In addition, we show that ΔIdsat for HKMG device is proportional to TSV diameter square, independent of TSV orientation, device polarity, and device distance from TSV.

A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration

A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (V_cc) of 1.8V, and a leakage current (I_LK) below 1 fA/μm² under +/-2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/μm², respectively, with their corresponding I_LK below 0.48, 0.19 and 0.09 fAmp/μm². Process reliability related defect density (D₀) of the interposer HK-MiM is as low as 0.095% cm^-2 as judged by a 10 years lifetime breakdown voltage (V_bd) criterion at V_cc=3.2V. This low D₀ ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm² within the Si interposer. Moreover, the V_bd tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., I_LK & V_bd tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.

An ultra-thin interposer utilizing 3D TSV technology

To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200 μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer.

A high-performance low-cost chip-on-Wafer package with sub-μm pitch Cu RDL

A low-cost and manufacturable 3D IC substrate-less Chip-on-Wafer (CoW) package has been studied. The new structure is a result of process simplification from the production-proven Chip on Wafer on Substrate (CoWoS™) technology. It features three layers of submicron (0.8μm pitch) Cu RDL on a Si interposer. High interposer yield is ensured with the excellent FAB-grade low defect density as demonstrated from good continuity of long RDL chains. Two layers of backside RDL are used to redistribute the IO from TSV at 0.2 mm pitch to BGA at 0.6 mm pitch. With the same multi-die integration capability as in CoWoS™, the CoW package has additional advantages of lower z-height, better thermal dissipation, and lower cost. Moreover, mechanical and thermal simulations reveal a relatively greater life cycle endurance for temperature cycling on board (TCoB) test. The CoW package passed preliminary component-level reliability assessments including μHAST, HTS and TC. This provides a promising CoWoS™ alternative for lower cost and thinner package with improved thermal performance. It also possesses the flexibility to combine with fan-out technology to be fitted in applications requiring higher IO count or larger BGA pitch.

High density 3D fanout package for heterogeneous integration

Three-dimensional (3D) fanout package stacking offers new levels of performance, high-density integration, and form factor advantages. Known-good fanout packages are stacked, and the vertical connection is built through Cu pillars in the molding area and solder bumps. Compared to existing TSV-based 3D integrated circuits (3DIC) technology, this solution reduces thermal crosstalk when integrating devices of different die sizes. Fanout package stacking potentially provides a cost-effective platform for highly flexible heterogeneous integration of digital, memory, analog, radio-frequency (RF) and optical devices.