Kuo-Nan Yang

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (µ-bump) processes and joining, that form the building blocks for 3D IC technology were developed based on established Si foundry technologies. Test vehicles (TVs) have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme.

Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking

High density through-silicon-via (TSV) and cost-effective 3D die-to-wafer integration scheme are proposed as best-in-class foundry solutions for high-end CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning of the TSV wafer and die-to-wafer assembly. The impact of extreme thinning on device threshold voltage, leakage currents, and Ion-Ioff characteristics of bulk CMOS devices with and without e-SiGe/CESL stressors has been minimized. The presence of TSV caused no significant changes in Cu/ELK reliability. These excellent characteristics suggest the 300mm 3D-IC processes are promising and suitable for adoption in next generation integrated circuits and interconnects.

High-aspect ratio through silicon via (TSV) technology

The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm × 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm × 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.

Orthotropic stress field induced by TSV and its impact on device performance

An orthotropic stress field was observed in the vicinity of the Cu-filled TSV on nominal (100) silicon substrate from both μRaman measured data and validated FEM result. The orthotropic elastic behavior of silicon in the (100) plane is believed to be the reason. The FEM model was further validated by the comparison with the measured electrical data, and used to predict the device performance shift under the influence of the TSV-induced stress. The performance shift pattern also showed an orthotropic pattern. This finding has profound implication on 3D silicon stacking design rule and system integration.

An ultra-thin interposer utilizing 3D TSV technology

To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200 μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer.

High performance 0.1 /spl mu/m PD SOI tunneling-biased MOSFETs (TBMOS)

Proposes a new structure of partially-depleted SOI MOSFETs tunneling-biased MOSFETs (TBMOS). In this structure, the floating body potential is pulled up by the carriers which tunnel from specially doped polysilicon gate to the floating body. Compared with bulk MOSFET (represented by body grounded device), TBMOS produces excellent swing (/spl sim/66 mV/dec), and >15% increase in I/sub D,SAT/. TBMOS also has better hot carrier immunity than body grounded device.