Doug C. H. Yu

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (µ-bump) processes and joining, that form the building blocks for 3D IC technology were developed based on established Si foundry technologies. Test vehicles (TVs) have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme.

Reliability evaluation of a CoWoS-enabled 3D IC package

TSV (Through Silicon Via)-based interposer has been proposed as a multi-die package solution to meet the rapidly increasing demand in inter-component (e.g. CPU, GPU and DRAM) communication bandwidth in an electronic system. The stacked-silicon die package configuration may give rise to package reliability concerns not observed in conventional monolithic flip-chip packages. 3D finite element method (FEM) was used to study the thermo-mechanical response of the interposer-based package during thermal cycle reliability stressing. Fatigue failures of the C4 and BGA joints are the two primary reliability focuses in the present study. Experimental data collected on the CoWoS™-enabled test vehicles were used to validate the FEM models. Parametric study of key package material and geometric parameters was performed to analyze their effects on C4 bump thermal cycle reliability. Package materials of interest include UF (underfill), lid and substrate, and the geometric parameters include lid thickness and C4 bump scheme. The results showed that the CoWoS package using AlSiC lid has better C4 bump life than the CoWoS package using Cu lid, and when the Tg of the underfill of C4 bump is higher, the C4 bump has better reliability. Furthermore, 3D thermo-mechanical and reliability study of BGA balls is presented for organic and ceramic substrates. Several DOEs have been constructed for ceramic substrate to increase BGA reliability by optimizing C4 underfill material and package design. The effect of board layer count and design is detailed. Finally reliability of BGA balls, C4 and micro-bumps are compared for a part that is mounted on a PCB board.

Array antenna integrated fan-out wafer level packaging (InFO-WLP) for millimeter wave system applications

Array antenna integrated with RF chip using InFO-WLP technology is proposed for millimeter wave system applications. Aperture-coupled patch antenna is designed on the fan-out molding compound (MC). The performance of single-element antenna is evaluated first and proved to have 5 dBi of gain. Meanwhile, the interconnect from chip to antenna feeding line is demonstrated to only have 0.7 dB loss, which can save 19 % PA output power compared with that of flip-chip package. Finally, the system performance of 4 × 4 antenna array integrated with RF chip on the InFO structure shows 14.7 dBi of array gain in a small form factor of 10 × 10 × 0.5 mm3.

Orthotropic stress field induced by TSV and its impact on device performance

An orthotropic stress field was observed in the vicinity of the Cu-filled TSV on nominal (100) silicon substrate from both μRaman measured data and validated FEM result. The orthotropic elastic behavior of silicon in the (100) plane is believed to be the reason. The FEM model was further validated by the comparison with the measured electrical data, and used to predict the device performance shift under the influence of the TSV-induced stress. The performance shift pattern also showed an orthotropic pattern. This finding has profound implication on 3D silicon stacking design rule and system integration.

Study of the thermo-mechanical behavior of glass interposer for flip chip packaging applications

The reliability of flip chip packages using either glass or organic substrate, and then mounted on printed circuit board (PCB) was investigated. This study is focused on the high stress concentration areas in the package structures and identified the stress mitigation solutions. Four-point bending test revealed that the fracture strength of the glass with through glass vias (TGV) can be significantly reduced by 10∼30% with respect to the different via densities. The brittle nature of glass along with its low fracture strength, particularly with TGV, could have serious implications on the reliability of the packaging system using glass substrate. In order to increase its fracture strength, the glass surface was coated with a low CTE film and is shown to effectively strengthen the glass. The assembled glass substrate packages subjected to thermal stressing were simulated by finite element modeling. To reduce the high stress concentration and improve the stress distribution in the glass interposer system, the parametric factors on the structure, materials, geometry and shape were investigated. According to our simulation result, the CTE of glass substrate is critically important in affecting the stress levels in the Si die, BGA ball and glass itself. To minimize the stress levels occurring on either side of the package structure, glass substrate with a medium CTE (∼8.3 ppm) is demonstrated as the optimal choice when sandwiched between the Si die (CTE∼2.7 ppm) and PCB board (CTE∼16 ppm) with C4 and BGA balls, respectively. Since the glass CTE can be tailored by adjusting its compositions, glass with an optimal CTE can be manufactured by the supplier.

Comparison of the electromigration behaviors between micro-bumps and C4 solder bumps

As flip chip packages continue to migrate to Pb-free solder and micro-bumping (μbump) for 3D IC stacking, achieving high reliability with reduced dimension and concurrent increase in current density has become one of the major challenges for microelectronic packaging systems. In this study, the electromigration (EM) performance of the nominal C4 and μbump is compared. During EM tests, the resistance increase in μbumps is mainly due to intermetallic compound (IMC) growth, in contrast to the void formation and UBM/ IMC dissolution in C4 bumps. Early EM failures which were frequently observed in C4 bumps were mostly eliminated in the μ bump structures. Stress modeling was correlated with experimental observations. A proper design of the bump schemes can effectively distribute the current more uniformly, thus reducing the current crowding and local joule heating effects. Moreover, Sn grain orientation was found to critically affect the EM performance of both the μbump and the C4 bump joints.

Process development to enable 3D IC multi-tier die bond for 20μM pitch and beyond

We demonstrate for the first time 3D multi-tier (N=4) 50μm thin die bonding for 3D IC technology using low bonding temperature and pressure for Cu TSVs bonded on Cu bumps with a cost effective structure. Die-to-die (D2D) thermal compression bonding (TCB) process with scrubbing is carefully studied in order to improve the bump height TTV and surface roughness. The bonding temperature and pressure can also be reduced significantly to below 220C and 100MPa. The standalone thin die warpage initially 15μm is reduced to 5.4μm by applying the optimized TCB process. The electrical characterizations show good daisy chain connections between each stacked chip and the resistances are very close to the theoretical values. The cross section SEM proofs good TSV alignment to Cu bump, and TSV nails deform and land nicely onto the Cu bump. Finally, we propose to move forward to die-to-wafer approach and migrate to 10μm bump pitch for advanced package application.

New System-in-Package (SiP) Integration technologies

New System-in-Package (SiP) with innovative Wafer-Level-System-Integration (WLSI) technologies that leverage foundry core competence on wafer processes have been demonstrated. The WLSI technologies include Chip-on-Wafer-on-Substrate (CoWoSTM) 3DIC and interposer, Integrated Fan-Out (InFO) and Chip-Scale Wafer-Level-Packaging. Wide application portfolio from very low I/O pin-count, low-cost devices, to medium, high and ultra-high pin-count are realized. Chip-partition followed by flexible powerful integration of single-chip or multi-chips, advanced or matured Si, logic and memory, SoC and sensor/MEMS. System values include low profile, low power, high bandwidth along with competitive cost can be readily achieved. With the chip-partition, we can sustain Moores law longer.

300mm size ultra-thin glass interposer technology and high-Q embedded helical inductor (EHI) for mobile application

The first publication on fabrication of a 300 mm size, 50 μm ultra-thin glass interposer is presented. According to measured data and modeling analysis, merits of on-glass inductors and transmission lines outperform those of on-silicon in Q-factor, power dissipation, and power/signal integrity. Glass interposer is a promising building block technology for future hybrid mixed signal heterogeneous chip integration solution.

A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration

A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (V_cc) of 1.8V, and a leakage current (I_LK) below 1 fA/μm² under +/-2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/μm², respectively, with their corresponding I_LK below 0.48, 0.19 and 0.09 fAmp/μm². Process reliability related defect density (D₀) of the interposer HK-MiM is as low as 0.095% cm^-2 as judged by a 10 years lifetime breakdown voltage (V_bd) criterion at V_cc=3.2V. This low D₀ ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm² within the Si interposer. Moreover, the V_bd tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., I_LK & V_bd tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.