Jack T. Kavalieros

Benchmarking nanotechnology for high-performance and low-power logic transistor applications

Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronic applications. In particular, several emerging nanoelectronic devices such as carbon-nanotube field-effect transistors (FETs), Si nanowire FETs, and planar III-V compound semiconductor (e.g., InSb, InAs) FETs, all hold promise as potential device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moores Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this paper, we use four key device metrics to compare these emerging nanoelectronic devices to the state-of-the-art planar and nonplanar Si logic transistors. These four metrics include: 1) CV/I or intrinsic gate delay versus physical gate length L/sub g/; 2) energy-delay product versus L/sub g/; 3) subthreshold slope versus L/sub g/; and 4) CV/I versus on-to-off-state current ratio I/sub ON//I/sub OFF/. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome. We believe that benchmarking is a key element in accelerating the progress of nanotechnology research for logic transistor applications.

Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS and PMOS trigate transistors are demonstrated with IDSAT=1.4 mA/mum and 1.1 mA/mum respectively (IOFF=100nA/mum, VCC =1.1V and LG=40nm) with excellent short channel effects (SCE)-DIBL and subthreshold swing, DeltaS. The contributions of strain, the lang100rang vs. lang110rang substrate orientations, high-k gate dielectrics, and low channel doping are investigated for a variety of channel dimensions and FIN profiles. We observe no evidence of early parasitic corner transistor turn-on in the current devices which can potentially degrade ION-IOFF and DeltaS

A 50 nm depleted-substrate CMOS transistor (DST)

In this paper we show a Depleted-Substrate Transistor (DST) technology which demonstrates significant performance gain over bulk Si transistors without the floating body effect (FBE). We have fabricated depleted-substrate CMOS transistors on thin silicon body (/spl les/30 nm) with physical gate lengths down to 50 nm which show much steeper subthreshold slopes (/spl les/75 mV/decade) and improved DIBL (/spl les/50 mV/V) over both partially-depleted (P-D) SOI and bulk Si, for both PMOS and NMOS transistors. The salicide formation and high parasitic resistance problems associated with the use of thin Si body can be overcome by using raised source/drain. Depleted-substrate PMOS transistors with 50 nm physical gate length and raised source/drain were fabricated and achieved I/sub on/=0.65 mA/um and I/sub off/=9 nA/um at V/sub cc/=1.3 V. This PMOS drive current is the highest ever reported, and is about 30% higher than any previously published PMOS I/sub on/ value for both PD-SOI and bulk Si at a given I/sub off/. The use of raised source/drain improved the I/sub on/ of the depleted-substrate NMOS transistors by /spl sim/20%. Depleted-substrate NMOS transistors with 65 nm physical gate length and raised source/drain achieved DIBL=45 mV/V, subthreshold slope=75 mV/decade, I/sub on/=1.18 mA/um and I/sub off/ =60 nA/um at V/sub cc/=1.3 V, as well as significant improvement in Id-Vd characteristics due to a 60% reduction in DIBL and >25% improvement in subthreshold slope over the bulk Si.

30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

Planar CMOS transistors have been fabricated to evaluate the 70 nm technology node using conventional transistor design methodologies. Conventional CMOS transistors with 30 nm physical gate length were fabricated using aggressively scaled junctions, polysilicon gate electrode, gate oxide and Ni silicide. These devices have inversion Cox exceeding 1.9 /spl mu/F/cm2, n-MOS gate delay (CV/I) of 0.94 ps and p-MOS gate delay of 1.7 ps at V/sub cc/=0.85 V. These are the smallest CV/I values ever reported for Si CMOS devices. The transistors also show good short channel control and subthreshold swings. The n-MOS and p-MOS have drive currents equal to 514 /spl mu/A//spl mu/m and 285 /spl mu/A//spl mu/m respectively with I/sub off/ at or below 100 nA//spl mu/m at Vcc=0.85 V. The saturation gm is equal to 1200 mS/mm for n-MOS and 640 mS/mm for p-MOS. These are among the highest gm values ever reported. The junction edge leakage is reasonably low with less than 1 nA//spl mu/m at 1.0 V and 100 C for both n-MOS and p-MOS. These encouraging results suggest that the 70 nm technology node is achievable using conventional planar transistor design and process flow.

BTI reliability of 45 nm high-K + metal-gate process technology

In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.

Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit

Accurate measurement of MOS transistor inversion capacitance with a physical silicon dioxide thickness less than 20 /spl Aring/ requires correction for the direct tunneling leakage. This work presents a capacitance model and extraction based on the application of a lossy transmission line model to the MOS transistor. This approach properly accounts for the leakage current distribution along the channel and produces a gate length dependent correction factor for the measured capacitance that overcomes discrepancies produced through use of previously reported discrete element based models. An extraction technique is presented to determine the oxides tunneling and channel resistance of the transmission line equivalent circuit. This model is confirmed by producing consistent C/sub 0x/ measurements for several different gate lengths with physical silicon dioxide thickness of 9, 12, and 18 /spl Aring/.

High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture

In this article we demonstrate a Ge p-channel QWFET with scaled TOXE = 14.5Å and mobility of 770 cm2/V*s at ns =5×1012 cm−2 (charge density in the state-of-the-art Si transistor channel at Vcc = 0.5V). For thin TOXE < 40 Å, this represents the highest hole mobility reported for any Ge device and is 4× higher than state-of-the-art strained silicon. The QWFET architecture achieves high mobility by incorporating biaxial strain and eliminating dopant impurity scattering. The thin TOXE was achieved using a Si cap and a low Dt transistor process, which has a low oxide interface Dit. Parallel conduction in the SiGe buffer was suppressed using a phosphorus junction layer, allowing healthy subthreshold slope in Ge QWFET for the first time. The Ge QWFET achieves an intrinsic Gmsat which is 2× higher than the InSb p-channel QWFET [3]. These results suggest the Ge QWFET is a viable p-channel option for non-silicon CMOS.

Silicon nano-transistors and breaking the 10 nm physical gate length barrier

In this paper, the performance and energy delay trends for research devices down to 10 nm and also discusses the 10 nm barrier and potential ways to break it were explored.

Gate dielectric scaling for high-performance CMOS: from SiO 2 to high-K

We have successfully demonstrated very high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p- and n-channels on bulk Si. We believe that high-K/metal-gate is an option for the 45 nm high-performance logic technology node.

Silicon nano-transistors for logic applications

Abstract Silicon transistors have undergone rapid miniaturization in the past several decades. Recently reported CMOS devices have dimensional scales approaching the “nano-transistor” regime. This paper discusses performance characteristics of a MOSFET device with 15 nm physical gate length. In addition, aspects of a non-planar CMOS technology that bridges the gap between traditional CMOS and the nano-technology era will be presented. It is likely that this non-planar device will form the basic device architecture for future generations of nano-technology.