Chihiro J. Uchibori

SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET

We have developed a robust latch for achieving high reliability in LSI. The latch can attenuate multi-node single-event-upset (MNSEU) and single event transient on local-clock (SETLC). The robust latch has Dual-clock-buffers (DCB) and Double-height-cell (DHC) technologies. Results on neutron acceleration experiments show that DHC can dramatically attenuate MNSEU and DCB can protect almost SETLC of the latch. In addition, we investigate optimum design in well structure.

Effects of Chip-Package Interaction on Mechanical Reliability of Cu Interconnects for 65nm Technology Node and Beyond

The impact of chip-package interaction (CPI) on the mechanical reliability of Cu low-k interconnects was investigated using a 3D multi-level sub-modeling method. The analysis was focused on the die attach process for Pb-free solder where a high thermal load will occur during solder reflow before underfilling to maximize the packaging effect. We compared first the CPI for a CVD-OSG (k=3.0) with MSQ (k=2.7) and spin-on polymer (k=2.7) to investigate how better material properties can improve interconnect reliability. Then the study was extended to porous MSQ (k=2.3) to examine CPI for the 65nm node and beyond. Finally, requirements of the mechanical properties of low-k ILD for improving interconnect reliability are discussed

Chip Package Interaction analysis for Cu/Ultra low-k large die Flip Chip Ball Grid Array

The impact of Chip-Package Interaction (CPI) which is caused by the mismatch in the coefficient of thermal expansion (CTE) between substrate and chip in a Flip Chip Ball Grid Array (FCBGA) on the mechanical reliability of Cu/Ultra low-k in a larger die was investigated using Finite Element Analysis (FEA). In order to associate the deformation and thermal stresses in FCBGA with those in the Cu/Ultra low-k structure which has a large difference of dimension, multi-step sub-modeling technique was used. The energy release rate (ERR) which indicates the driving force for delamination at the specific interfaces in Cu/Ultra low-k structures was calculated using modified virtual crack closure (MVCC) method to assess the mechanical reliability. The ERR at the different interfaces in four metal layers (M1 to M4) model were calculated to find the effect of mechanical properties of dielectrics on CPI. The ERR at the interface in the upper layer was higher than that at the lower layer, when ultra low-k is used in M1 and M2 layers and SiOC is used in M3 and M4 layers. However, the ERR at M4 interface becomes about 33% lower when SiO2 is used in M4 level. This result indicates that the mechanical properties of dielectrics are important to control CPI. Then, the ERR of nine metal layers (M1 to M9) model was calculated to improve the accuracy of simulations where the dimension of interconnect structures were determined by the design rule for 90nm technology node. In this model, the ERR at M9 layer decreased significantly with W trench between A1 pad and M8 layer which indicates that the interconnect structure affects the CPI. Finally, the bump layout impacts on CPI were investigated. The highest equivalent stress near the under bump material (UBM) of the outer most solder bump was reduced about 20% by placing two extra solder bumps next to it. This result indicates that the layout of solder bump affects CPI, as well. Based on these study, the guideline to improve the mechanical reliability of Cu/Ultra low-k Interconnect in FCBGA by the material selection for interconnect and by optimizing the interconnect structure and the bump layout will be discussed.

Impact of Thermomechanical Stresses on Bumpless Chip in Stacked Wafer Structure

Crack formation due to thermomechanical stresses generated by a dielectric polymer thicker than 20 µm and by that with high modulus during the bumpless chip-on-wafer (COW) process has been investigated. According to the stress simulation, thermal stresses increase with polymer thickness where the stress value ranges from 100 to 200 MPa for benzocyclobutene (BCB)-based resin. Thermal stresses in the hybrid structure using epoxy-based resin and BCB-based resin were calculated to be less than 100 MPa. Thus, the reduction of the thicknesses of the polymer as well as the Si chip was found to be effective in avoiding crack formation in the COW structure. Moreover, to investigate the crack driving force, the energy release rate (ERR) was calculated. The crack propagates toward the Si chip corner and the result is consistent with the experiment. On the COW structure, a thin Si chip and a low-modulus polymer expand the process window.

Impact of chip package interaction on Cu/Ultra low-k interconnect delamination in Flip Chip Package with large die

Die size effects on Chip Package Interaction for Cu/Ultra low-k interconnect in Flip Chip Package were investigated using mechanical and thermal analysis. The analytical and the theoretical study suggested that the die size effects were not caused only by the mismatch in CTE between die and substrate. By considering the number of bonding solder and its mechanical property during the cooling process, the die size dependency of CPI was successfully demonstrated.

Impact of Cu/low‐k Interconnect Design on Chip Package Interaction in Flip Chip Package

The impacts of Cu/low‐k interconnect structures and solder bump layouts on Chip Package Interaction (CPI) in Flip Chip Ball Grid Array (FCBGA) was investigated. The energy release rates (ERR) that indicate the driving force for delamination were calculated to evaluate the impact of CPI on mechanical reliability of Cu/low‐k in FCBGA. First, two metal layer interconnect structure was modeled to find the effects of the mechanical properties of inter layer dielectric (ILD) materials on ERR. The ERR was found to increase rapidly when the modulus of ILD is lower than 10 GPa. Then the number of the interconnect layer was increased to four to find the impact of wiring dimensions on CPI. The ERR at the upper interface were consistently higher than those of lower interface. However, when TEOS is used for M4 level, low‐k is used for M3 and Ultra low‐k is used for M2 and M1 level, the ERR at M3 level becomes higher than that at M4 level. The wiring dimension and mechanical properties of ILD were found to be important...

Direct Attach of Photonic Components on Substrates With Optical Interconnects

Direct attach of lasers and photodiodes on boards with optical interconnects can facilitate high-density packaging of high-speed optical components. For the technology demonstration, test chips are assembled by means of optical polymer pillars on substrates with embedded arrays of waveguides (WGs) and 45deg mirrors. The light couples vertically though the optical pillars enabling 1.5-dB reduction of the WG-to-chip coupling loss to 0.5dB. The insertion loss of the module tested is less than 2 dB and 10-Gb/s signal transmission through the module is demonstrated with bit-error rate <10-12. Three-dimensional finite-element analysis provides results on the stress distribution in the displaced pillars of different shapes

Structural effects on Chip Package Interaction and mechanical reliability of Cu/low-k multi-layer interconnects in flip-chip package

The effects of structural design on the mechanical reliability of Cu/low-k multi-layer interconnects are investigated using finite element method. The Chip Package Interaction (CPI) was analyzed for a model of twelve wiring layers to calculate the energy release rate (ERR). The relations between the feature dimensions, such as copper interconnect width and low-k dielectric thickness, and the interfacial fracture are studied. Also, implications on the design rules for interconnect and reliability are discussed.

Investigation of Mechanical Reliability of Cu/low-k Multi-layer Interconnects in Flip Chip Packages

The impact of chip-package interaction (CPI) on the reliability of Cu/low-k interconnects in a flip-chip package for high performance ULSI was investigated using finite element analysis (FEA). A 3D four-level sub-modeling approach was used to analyze the CPI to link the deformation from the package level to the interconnect level. The energy release rate (ERR) and fracture mode at critical interface were calculated using a A modified virtual crack closure technique (MVCC). The simulation was focused on the die attach process for Pb- free process before underfilling where the maximum CPI effect is expected. First the general characteristics of CPI were analyzed for interfaces in two metal-layer interconnects. The ERR was found to increase rapidly with decreasing modulus of Inter Layer Dielectric (ILD) although the effect of CTE of ILD was found to be small. Next, the CPI for a four metal-layer structure was investigated. Here the ERR for upper M3 and M4 levels were consistently higher than those of lower Ml and M2 levels. If the same low-k ILD is used for all layers, the M4 interfaces show 2.5 times higher ERR than the lower levels. However, when TEOS is used in the M4 level, the ERR at M3 interfaces becomes 35% higher than the M4 level. The wiring dimensions and ILD properties were found to be important in controlling CPI. The CPI impact on ultra low-k reliability and interconnect design rules for the 65 nm technology and beyond are discussed.

Effects of Chip‐Package Interaction on Mechanical Reliability of Cu Interconnects

The impact of chip-package interaction (CPI) on the mechanical reliability of Cu low-k interconnects was investigated using a 3D multi-level sub-modeling method. The analysis was focused on the die attach process for Pb-free solder where a high thermal load will occur during solder reflow before underfilling to maximize the packaging effect. We compared first the CPI for a CVD-OSG (k=3.0) with MSQ (k=2.7) and spin-on polymer (k=2.7) to investigate how better material properties can improve interconnect reliability. Then the study was extended to porous MSQ (k=2.3) to examine CPI for the 65nm node and beyond. Finally, requirements of the mechanical properties of low-k ILD for improving interconnect reliability are discussed