Yoriko Mizushima

Development of sub 10-µm ultra-thinning technology using device wafers for 3D manufacturing of terabit memory

200-mm and 300-mm device wafers were successfully thinned down to less than 10-µm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50-nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9-µm, switching charge showed no change by the thinning process. CMOS logic device wafers thinned to 7-µm indicated neither change in Ion current nor junction leakage current. Thinning such wafers to <10-µm will allow for lower aspect ratio less than 4 of Through-Silicon-Via (TSV) in a via-last process.

Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects

Influence of the sidewall roughness in through-silicon via (TSV) on leakage currents has been studied. Micro steps along the sidewall, so-called scalloping, formed by Bosch etching, are strongly related to leakage currents between adjacent TSVs. Microcracks in the SiON barriers were observed by TEM analysis and correlated with the sidewall roughness. FEM simulations of the stress concentration along the sidewall roughness clarified the origin of cracking. A non-Bosch etching process showed smooth sidewall surface and we consider it to be feasible for reliable TSV interconnects.

Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects

High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7- µm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described. Properties examined include Kelvin and stack chain resistances of Cu interconnects as well as Ion-Ioff, threshold voltage shift, and junction leakage of transistors. It was found that the electrical properties were not affected by bonding, thinning and debonding process indicating good feasibility of 3D stacking integration to the strain and low-k technology.

Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology

Diffusion behavior of Cu in Cu through-silicon-vias (TSVs) fabricated using low-temperature plasma enhanced chemical vapor deposition (LT-PECVD) has been evaluated. Silicon oxynitride (SiON) barrier films were formed by LT-PECVD at 150 °C. Cu diffusion rate was found to increase with decreasing film density. The critical density and thickness for prevention of Cu diffusion into Si substrate have been estimated. In case of a film with density >60% of the bulk value and/or thickness >100 nm, no change of electrical resistance for stacked wafers containing TSVs was observed after 1000 cycles of thermal stress. According to above results, SiON film formed at 150 °C can be used for the TSV process without any degradation of electrical characteristics and reliability, enabling a reduction in total process temperature in the wafer-on-wafer technology.

Stress migration phenomenon in narrow copper interconnects

Stress migration (SM) behavior in Cu damascene interconnects was investigated in detail using different kinds of test patterns. SM failure was found in narrow lines that are very long, or connecting to a wide line. In the pattern in which narrow lines are connected to wide metal, the failure rate decreased as the narrow metal becomes longer. It was found that the failure rate in minimum 0.14μm wide lines is more than that in 0.2–0.42μm wide lines. The result of the test patterns with different via arrangements clarified that the placing of the vias at the edge of the M1 line plays an important role in the SM phenomenon in narrow copper lines. Failure analysis using scanning transmission electron microscopy revealed voiding beneath the via at the failure points for all test patterns. It is shown that the enhanced failure rate in the minimum wide lines and the via arrangement effect cannot be understood by the previous diffusion mechanism. Based on these results, the effect of the via arrangement close to t...

45 nm-node BEOL integration featuring porous-ultra-low-k/Cu multilevel interconnects

45 nm-node multilevel Cu interconnects with porous-ultra-low-k have successfully been integrated. Key features to realize 45 nm-node interconnects are as follows: 1) porous ultra-low-k material NCS (nano-clustering silica) has been applied to both wire-level and via-level dielectrics (what we call full-NCS structure), and its sufficient robustness has been demonstrated; 2) 70-nm vias have been formed by high-NA 193 nm lithography with fine-tuned model-based OPC and multi-hard-mask dual-damascene process - more than 90% yields of 1 M via chains have been obtained; 3) good TDDB (time-dependent dielectric breakdown) characteristics of 70 nm wire spacing filled with NCS has been achieved. Because it is considered that the applied-voltage (Vdd) of a 45 nm-node technology will be almost the same as that of the previous technology, the dielectrics have to endure the high electrical field. NCS in Cu wiring has excellent insulating properties without any pore sealing materials which cause either the k/sub eff/ value or actual wire width to be worse.

Simple Modeling and Characterization of Stress Migration Phenomena in Cu Interconnects

Many observations of stress-induced voids beneath vias in wide Cu lines have been performed to analyze stress migration phenomena. Most of the voids that caused fatal failures of circuits accompanied grain boundaries in the lower lines. Finite element method calculations were performed to obtain the stress distribution around a via sandwiched between wide upper and lower lines. Based on these results, a void growth model for the Cu stress migration phenomena has been proposed by applying the Hull and Rimmer theory. This model takes two diffusion paths, such as a grain boundary and a barrier/Cu interface, into consideration. Compared with experimental results, the proposed model successfully explained the mean time to failure dependence on the temperature and geometrical parameters of Cu interconnects.

Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

Ultrathin wafers, which enable the low-aspect-ratio through-silicon vias to be formed easily, are indispensable for bumpless three-dimensional (3D) stacking. To clarify thinning-induced damage in detail, atomic-level defects occurring during wafer thinning and due to mechanical stress at microregions of the fracture surface have been studied. Such damage was evaluated by µ-Raman spectroscopy, laser microscopy, transmission electron microscopy, and positron annihilation spectroscopy. Coarse (#320 grit) grinding causes a roughly 500 MPa compressive stress, resulting in the formation of a less than 5 µm defect layer. Fine (#2000 grit) grinding enables the formation of a plane surface and reduces the stress to 100–200 MPa. However, a damaged layer of 200 nm still remains and an almost 100-nm-thick layer of vacancy-type defects exists. After chemical mechanical polishing (CMP), a stress-free surface was obtained and no defects were found except atomic-level vacancies, which were detected in a layer of 4 nm thickness after 1 µm CMP.

Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications

An ultra-thinning down to 4-μm using 300-mm wafer proven by 40-nm Node 2Gb DRAM has been developed for the first time. Three different types of thinning process including coarse grinding, fine grinding, and stress relief were optimized and an atomic level vacancy less than 10-nm in depth at backside of wafer was formed successively. Thickness uniformity even after thinning down to 4-μm was approximately 1-μm within 300-mm wafer. No degradation in terms of retention characteristics and distribution employing 2Gb DRAM wafer was found after ultra-thinning. This suggests that no damage occurred due to thinning processes including wafer bonding and debonding steps. These results indicate good feasibility for multi-stack Wafer-on-Wafer (WOW) processes with the lowest aspect ratio of TSVs and parasitic capacitance, and enable multi-stacking for Tera-scale high density memory.

Investigation of stress-induced voiding inside and under VIAS in copper interconnects with “wing” pattern

Stress induce voiding (SIV) inside and under vias in copper interconnects with ldquowingrdquo-pattern were investigated for 90 nm and 65 nm node processes. The difference of two voidings are the resistance change during acceleration test and the diffusion path. However, common features were found between both types of voiding; the interconnect fails fast as the ldquowingrdquo area grows. Both types of voiding have a critical ldquowingrdquo area where failure never occurs. Both of voiding is more affected by diffusion source than by stress gradient.