Hideya Matsuyama

SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET

We have developed a robust latch for achieving high reliability in LSI. The latch can attenuate multi-node single-event-upset (MNSEU) and single event transient on local-clock (SETLC). The robust latch has Dual-clock-buffers (DCB) and Double-height-cell (DHC) technologies. Results on neutron acceleration experiments show that DHC can dramatically attenuate MNSEU and DCB can protect almost SETLC of the latch. In addition, we investigate optimum design in well structure.

Stress migration phenomenon in narrow copper interconnects

Stress migration (SM) behavior in Cu damascene interconnects was investigated in detail using different kinds of test patterns. SM failure was found in narrow lines that are very long, or connecting to a wide line. In the pattern in which narrow lines are connected to wide metal, the failure rate decreased as the narrow metal becomes longer. It was found that the failure rate in minimum 0.14μm wide lines is more than that in 0.2–0.42μm wide lines. The result of the test patterns with different via arrangements clarified that the placing of the vias at the edge of the M1 line plays an important role in the SM phenomenon in narrow copper lines. Failure analysis using scanning transmission electron microscopy revealed voiding beneath the via at the failure points for all test patterns. It is shown that the enhanced failure rate in the minimum wide lines and the via arrangement effect cannot be understood by the previous diffusion mechanism. Based on these results, the effect of the via arrangement close to t...

Stress induced failure analysis by stress measurements in copper dual damascene interconnects

Stress migration behavior in Cu dual damascene interconnects is investigated in detail. It is revealed that the failure rate depends on structural parameters such as line width and via diameter. X-ray diffraction is employed to measure the thermal stress in lines and vias. The stress difference between lines and vias is found to be related to the failure rate of multi-level interconnects. An effective method to suppress the failure is also demonstrated.

Simultaneous measurement of soft error rate of 90 nm CMOS SRAM and cosmic ray neutron spectra at the summit of Mauna Kea

We carried out simultaneous measurement of SERs and cosmic ray neutron spectra for the first time. We measured SERs using 90 nm CMOS SRAM chips and measured neutron spectra using a Bonner multisphere spectrometer. We carried out the SER field measurement at the 4200 m summit of Mauna Kea, which is the most suitable place for SER field measurements because the neutron flux is over 10 times greater there than that at sea level. Therefore, we could avoid making field measurements that usually require a long measuring time (about a year) to obtain sufficient accuracy.

Investigation of stress-induced voiding inside and under VIAS in copper interconnects with “wing” pattern

Stress induce voiding (SIV) inside and under vias in copper interconnects with ldquowingrdquo-pattern were investigated for 90 nm and 65 nm node processes. The difference of two voidings are the resistance change during acceleration test and the diffusion path. However, common features were found between both types of voiding; the interconnect fails fast as the ldquowingrdquo area grows. Both types of voiding have a critical ldquowingrdquo area where failure never occurs. Both of voiding is more affected by diffusion source than by stress gradient.

Investigation of multi cell upset in sequential logic and validity of redundancy technique

Purpose of this work is investigation of validity on redundancy techniques for soft-error mitigation in sequential elements such as flop-flops and latches. We have evaluated multi-cell-upset (MCU) in sequential elements through neutron acceleration experiments at Osaka Univ. We have calculated mitigation efficiency of the redundancy technique from the experimental results. MCU ratio increases with technology advancing. Validity of the redundancy technique is kept even on advanced technologies.

1st quantitative failure-rate calculation for the actual large-scale SRAM using ultra-thin gate-dielectric with measured probability of the gate-current fluctuation and simulated circuit failure-rate

We investigated the influence over intermittent SRAM failure by gate current, Ig, fluctuation for the first time. In this paper, we also describe the difference of SRAM failure due to Ig fluctuations between MOS transistors before and after stressing. We have quantitatively confirmed that Ig fluctuation causes SRAM failure.

Exploring Well-Configurations for Minimizing Single Event Latchup

This work experimentally studies single event latchup (SEL) prevention by altering well configurations. The well structures under consideration in this paper are ordinary twin-well structure, triple-well structure with deep N-well (DNW) and triple-well structure with deep P-well (DPW). Doping profiles are also varied in our experiments. Neutron irradiation tests for test chips fabricated in 55-nm and 90-nm bulk Si CMOS processes show that SEL can be suppressed with a DPW or a DNW well configuration and a high-dose implantation in the well. Among these, DPW was the most effective to eliminate SEL, and no SEL was observed throughout our irradiation tests in the SRAM with DPW in both 55-nm and 90-nm processes. In addition, DPW brings a desirable side effect of single event upset (SEU) reduction. A disadvantage is a cost to develop a DPW process. DNW is a common process option and hence it is easily adopted for SEL prevention, but we need to pay attention to the fact that DNW increases SEU rate. Increasing well doping in twin-well structure reduced SEL by 60%.

Neutron Shielding Effect of Stacked Servers and Its Impact on Reduction of Soft Error Rate

The shielding effect of stacked servers on terrestrial neutrons and its impact on soft error rate of the device in the server are studied. Shielding simulation using the PHITS code is performed with the model of stacked servers and demonstrates its strong effect on neutron attenuation. The measurement of terrestrial neutrons by a Bonner sphere neutron spectrometer is carried out in open air and in a building in order to compare the shielding contributions from stacked servers and from the building. This comparison shows that the neutron attenuation is mainly due to stacked servers depending on its location in the building. Finally, the soft error rate of a 28 nm SRAM cell implemented in CPUs of stacked servers is simulated through PHYSERD with circuit simulation. Our study reveals that the soft error rate is significantly suppressed by the neutron flux attenuation and the distortion of the energy spectrum, both of which are caused by the shielding effect of stacked servers.

Mitigating Multi-Bit-Upset With Well-Slits in 28 nm Multi-Bit-Latch

This paper proposes a technique that mitigates multi-bit-upset (MBU) in multi-bit-latch (MBL) without performance degradation by applying well-slits. The area overhead in an MBL macro for processor design, which includes a clock buffer and a checker, is only 5.4% in a 28 nm technology. Sixty-hour accelerated neutron irradiation test observed no MBUs in the MBL with well-slits. The proposed mitigation technique achieved excellent robustness against MBU without any increase in SBU rate. The MBL with the proposed mitigation technique helps improve reliability of electronic devices.