Jun Iwamura

A high speed and low power CMOS/SOS multiplier-accumulator

A high speed and low power 16-bit parallel multiplier, with an accumulator on a chip, which performs 16-bit × 16-bit multiplication plus 35-bit data accumulation in 45ns with 125mW power dissipation, is described. The chip uses a unique modified array scheme to reduce the number of adding stages of partial products while constructing a regular structure. The use of CMOS/SOS technology contributes to reductions in the die area (4.2mm square), power dissipation and operation time. Combination of the modified array scheme and CMOS/SOS achieved ECL speed with CMOS power.

A CMOS/SOS multiplier

A CMOS/SOS 16b x 16b parallel multiplier with a chip using a modified array to speed arithmetic, performing a 16b x 16b multiplication typically in 27ns, while dissipating 150mW power, will be reported. Functions and pin configuration of the chip have been designed to have upward compatibility with commercially available LSI multipliers*. Figure la shows a fraction of the multiplier array which uses a modified array technique’ in contrast to a conventional carry save adder shown in b . The array consists of odd rows and even rows. Sum and carry signals generated by an odd row are pansferred to the next odd row, and those of an even row are concurrently transferred to the next even row. Therefore, two pairs of sum and carry signal streams are prepared in the array in parallel. In the following stage, the sum of odd rows and of the even rows are added together to produce a final product. Since this modified array has reduced. the number of addition stages by about one half compared to the conventional carry save adder method, the maximum number of adder stages in a column required to accomplish any mode of 16b x 16b multiplication is only nine.

Design for testability of a 32-bit microprocessor-the TX1

Testable designs of the TX1, a 32-bit microprocessor based on the TRON architecture, are described. Clear testing strategies were developed, resulting in three testable design approaches implemented in an optimized form. Logic function test is composed of scan test and self test. Their efficiency is highly enhanced by the use of the bus structure or microinstruction set of the TX1. Fault coverage of over 90% is achieved by them with short testing time (several seconds) and small increase of chip area (4.2%). Design verification is done with scan test and macroblock test. The latter can directly test important manually designed hardware blocks independent of the complicated decode and control logic. The area increase is only 0.4%. It can give useful information for their refinement in the early phase of development.<<ETX>>

A sub nanosecond 8K-gate CMOS/SOS gate array

A CMOS/SOS 8370-gate array has been developed using a 2μm Si-gate process. Typical propagation delay time for the 2-input NAND gate with a fan out of 3 and 2mm of metal interconnect loading is 0.87ns.

Design of a 32 bit microprocessor, TX1

Implementation of the TX1 VLSI microprocessor is described. Particular emphasis is placed on the design method, which meets the requirements of short design time with reasonable chip size. A one-phase clock system, which is a better solution for high-speed operation but requires careful design for evading the skew problem, is discussed. Design for testability is embedded in the chip. The TX1 is fabricated with a 1.0 mu m two-layer metal CMOS process. The chip contains 450 K transistors in a 10.89*10.27 mm/sup 2/ die. >

Optimized design method for full-custom microprocessors

An effective design method for VLSI-based microprocessors is proposed. The chip is divided into three components, namely control logic, data paths, and macrocells, at a very early stage. The control logic is automatically designed by logic synthesis and automatic placement and routing. For the data paths and the macrocells, logic and layout are designed manually. By combining the design method with so-called design-pipelining, a 32-bit microprocessor with 460 K transistors was designed in a year without sacrificing the chip size and performance. The methods impact on design effort is also discussed

Implementation and evaluation of microinstruction controlled self test using a masked microinstruction scheme

A masked microinstruction scheme which reduces the size of the test microprogram used for a microinstruction-controlled self-test, a type of built-in self-test, is described. Implementation of the scheme applied to a 32-b microprocessor, the TX1, is illustrated, and its efficiency is discussed. Over 95% fault coverage for data path blocks in an execution unit is achieved, and almost all related control logic is tested with about 600 steps of test microprogram in the TX1. Without the scheme, it is estimated that the equivalent test requires about 1200 steps. Applicability of the scheme to other types of microprocessors is also discussed.<<ETX>>

4-&#181;m LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is7 \times 10^{-11}A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (VTD) to be -2.1 V. This is attributed to the higher temperature dependence of VTDthan that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.

A 7000-gate microprocessor on SOS&#8212;PULCE

An n-channel MOS LSI microprocessor integrating 20 000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process. It contains ALU, shifters, and 44 registers which are combined to three 16-bit buses. By utilizing three types of threshold voltage for load transistors, 28-percent reduction in power dissipation is achieved. The minimum cycle time is 200 ns. By using the Coplanar-II process, anomalous leakage currents due to parasitic transistors at the sides of island are suppressed. It is found that the silicon-on-sapphire (SOS) version operates 2.3 times faster than the bulk-silicon version, which is mainly explained by the parasitic capacitance ratio. Parallel-plate approximation in calculating a wiring capacitance results in an underestimate by a factor of 60 compared with taking the two-dimensional effect into account. It is verified that a) the observed yield of a very large SOS chip is higher than the value predicted from a randomly distributed defects model, and b) the yield-sensitive active area of an SOS is so small that it can compensate for the yield degradation due to the very large defects density on an SOS wafer.

Implementation and evaluation of the TRONCHIP specification for the TX1

Features of the TRONCHIP specification were analyzed and implemented to a newly developed 32-bit microprocessor, the TX1. Performance of the TX1 was measured from the view point of verification of the effectiveness of the TRONCHIP specification.