Shin-Yo Lin

Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation

Given a set of numbers X, finding the minimum value of X, min_1st, is a very easy task. However, efficiently finding its second minimum value, min_2nd, requires the derivations of min_1st and finding the minimum value from the set of the remaining numbers. Efficient algorithms and cost-effective hardware of finding the two smallest of X are greatly needed for the low-density parity-check (LDPC) decoder design. The following two architectures are developed in this paper: (1) sorting-based (XS) approach and (2) tree structure (TS) approach. Experimental results show that the XS approach provides less number of comparisons, while the TS approach achieves higher speed performance at lower hardware cost. Since the hardware unit is repeatedly used in the LDPC decoder design, the proposed high-speed low-cost TS approach is strongly recommended.

Efficient memory-based FFT processors for OFDM applications

This paper presents Radix-2 memory-based FFT (MBFFT) processors. Taking the advantages of low hardware cost of MBFFT architectures, this study improves the speed performance. The improvement was achieved by an efficient memory retrieval scheme for reducing the control complexity and a clock scheme with parallel structures for reducing the cycle times and latency. Instead of using dual-port memories for data storage and retrieval, our designs use single-port memories with pre-fetch registers for hardware cost reduction. Based on the pre-layout simulation results, the core area of the developed MBFFT is 2.04 mm with the maximal work frequency of 198 MHz for N=8192 points (24 bits per word).

Low-cost FFT processor for DVB-T2 applications

An efficient Fast Fourier Transform (FFT) processor is greatly needed for real-time operation in many OFDM applications, such as xDSL, DAB, DVB-T/H, and etc. This paper presents a low-cost Parallel Memory-based FFT (PMB-FFT) processor for DVB-T2 applications. The processor has been designed and implemented in 90nm 1P9M CMOS process. Experimental results show that the PMB-FFT processor meets the DVB-T2 standard with N=32,768 points, and takes only 2.51 mm2 in the core area with a power consumption of 0.89 mW at 25MHz.

Efficient Memory-Based FFT Architectures for Digital Video Broadcasting (DVB-T/H)

An efficient FFT (fast Fourier transform) processor is greatly needed for real-time operation in many OFDM applications, such as xDSL, DAB, DVB-T/H, and etc. This study developed four types of efficient memory-based Radix-2 FFT architecture with a memory size of N words for N-point FFT operations. The latency can be improved from (N/2)+(N/ 2)logN, to (N/2+2)+(N/4)logN, further to [N/2+2]+(N/8) logN, at the cost of increased hardware. Results show that the developed parallel memory-based architecture can achieve a latency of 140 us with 2.425 mm2 in area for N=8192, which is well suitable for being implemented in DVB-T/H.

High-speed, Low Cost Parallel Memory-Based FFT Processors for OFDM Applications

Low cost yet efficient FFT (Fast Fourier Transform) processors are greatly needed for real-time operation in many OFDM applications. Taking the advantages of both memory-based and pipelined FFT architectures, this paper presents simple radix-2 memory-based FFT (MBFFT) Processors with low hardware cost and high maximum operation frequency. Results show that the core area of the proposed MBFFT is 1.79 mm2 with the maximum operation frequency of 205 MHz, or a process speed of 269 mus for N=8192 points (24 bits per word). This also implies a throughput of 730 Mb/s (Mbits per second). This paper also presents parallel MBFFT structures with two and four butterfly processing elements (PEs), respectively, to improve the latency while still keeping low hardware cost and high maximum operation frequency.

Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications

This paper presents a radix-2 memory-based FFT processors, namely, MBFFTP, with a memory size of N words for large N complex points, where each word contains 24 bits. The developed MBFFTP meets DVB-T standard and can handle both 2K and 8K modes in the same architecture. The processors have been designed and implemented in TSMC 0.18mum 1P6M process. Results show that simple MBFFTP achieves a maximum work frequency of 173MHz, where its core chip area is approximately 1.80 mm with a core power consumption of 40.80 mW at 55 MHz for 2K mode and 48.16 mW at 65 MHz for 8K mode.

A low-cost continuous flow parallel memory-based FFT processor for Ultra-Wideband (UWB) applications

In the UWB systems, the data symbols are transmitted and received continuously. This study developed a continuous flow parallel memory-based FFT processor (CF-FFT processor) for UWB applications. Results show that the developed CF-FFT processor takes approximately 2.62 mm2 to achieve a operation rate of 1.096 GS/s (Gega Samples per second), where the TSMC 0.18 um 1P6M CMOS process was employed.

A Low-Cost Continuous-Flow FFT Processor for UWB Applications

In UWB systems, the data symbols are transmitted and received continuously. This study developed a continuous flow parallel memory-based FFT processor (CF-FFT processor) for UWB (ultra wideband) applications. Results show that the developed CF-FFT processor takes approximately 1.31 mm2 to achieve a throughput rate of 1 GS/s, where TSMC0.18 um 1P6M CMOS process was employed.

VLSI implementation of residue-to-binary converters for digital signal processing

The residue number system (RNS) provides an attractive alternative to traditional weighted number systems for high speed digital signal processing (DSP) and communication applications. To interface with the digital system, where the binary numbers are employed, the RNS-based processors require the conversions between binary form to the residue representation. This paper presents a simple conversion algorithm and hardware implementation for any arbitrary moduli sets {2kn ,2n-1,2n+1}, where k is a positive integer. The converter hardware includes nothing but (2n) converting units, where each unit is comprised of a 1-bit FA (full adder), a 2-to-1 MUX (multiplexer), and two latches. Experimental results show that, for n=6 and k=2, the converter takes only an area of 16,968 um with a delay of 14.20 ns, and, for n=8 and k=4, the area is 22,624 um2 with a delay of 19.54 ns, where the TSMC 0.18 um 1P6M process were employed. Both area and speed performances are significant.

Iterative decoding of JPEG coded images with channel coding in bit-rate analysis

We investigate iterative decoding of JPEG coded images combined with channel coding in bit-rate over noisy channels. The bit-rates and forward error correction are considered in different channel conditions. The bit-rate can be produced different image quality and data. The lower bit-rate presents the worse image quality, but the image data is less. However, the channel encoder gives a little error protection after the source encoder. The turbo decoder can produce a good image quality by several iterations. By these iterations mechanism, the lower bit-rate compression also presents a good image quality after source decoding. The increase the number of iteration gains the average of the PSNR up to 8-9 dB in the same bit-rate in the channel conditions. We propose the lower bit-rate image quality also achieving the corresponding performance than high bit-rate image quality by the corresponding iterations. The minor performance of the PSNR can be improved more than 5 iterations. Therefore, the iterative decoding scheme can be achieved in a real-time system.