Chin-Lung Cheng

Current-conduction and charge trapping properties due to bulk nitrogen in HfOxNy gate dielectric of metal-oxide-semiconductor devices

This work examined the effects of bulk nitrogen in HfOxNy gate dielectric on current-conduction and charge trapping of metal-oxide-semiconductor devices. The nitrogen concentration profiles in HfOxNy gate dielectric were adjusted by Hf target sputtered in an ambient of modulated nitrogen flow. The current-conduction mechanisms of HfOxNy film comprised of various nitrogen concentration profiles at the low- and high-electrical field were dominated by Schottky emission and Frenkel–Poole emission, respectively. The trap energy level involved in Frenkel–Pool conduction was estimated to be around 0.8 eV. Smaller stress-induced leakage current and flat-band voltage shift were obtained for devices with HfOxNy dielectric containing less bulk nitrogen, attributable to less interface strain∕stress and bulk trap.

Effects of denuded zone of Si(111) surface on current conduction and charge trapping of HfOxNy, gate dielectric in metal-oxide-semiconductor devices

This work investigated the effects of interstitial oxygen [Oi] defects at the Si(111) surface on current conduction and charge trapping of metal-oxide-simiconductor devices with HfOxNy gate dielectric. Smaller gate leakage current, stress-induced leakage current (SILC) and defect generation rate, attributable to the decrease of [Oi] defect concentration at the HfOxNy∕Si interface, were observed for devices with denuded zone. The current-conduction mechanism of the HfOxNy films at the low- and high-electrical field was dominated by the Schottky and Frenkel–Poole emissions, respectively. The trapped charges in HfOxNy dielectric were positive. The mechanism related to the SILC at low-electrical field can be explained using the interface trap-assisted tunneling.

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si(111) interface on current conduction and charge trapping of MOS devices

Low interstitial oxygen [O/sub i/] defects at the Si surface were formed by combination of rapid thermal/furnace annealing. The trap energy level involved in Frenkel-Pool conduction was estimated to be around 0.5 eV. Smaller gate leakage current, SILC and defect generation rate, but higher TM, attributable to the decrease of [O/sub i/] defect concentration at the HfO/sub x/N/sub y//Si interface, were observed.

Process techniques and electrical characterization for high-k (HfO/sub x/N/sub y/) gate dielectric in MOS devices

Effects of nitrogen concentration profiles in HfO/sub x/N/sub y/ on the electrical properties of metal-oxide-semiconductor (MOS) devices were investigated. The nitrogen concentration profiles in HfO/sub x/N/sub y/ gate dielectric was adjusted by sputtering the Hf target in ambient of modulated nitrogen flow. The trapped charges in HfO/sub x/N/sub y/ dielectric are positive. The current-conduction mechanisms of HfO/sub x/N/sub y/ film at the low- and high-electrical field are dominated by Schottky emission and Frenkel-Poole emission, respectively. The mechanism relevant to the relatively larger stress induced leakage current (SILC) at low electrical fields can be explained by the trap-assisted tunneling. On the other hand, the relatively smaller leakage current found at high electric fields can be attributed to the electron trapping in bulk defects. Smaller flat-band voltage shift and SILC are observed for devices with HfO/sub x/N/sub y/ dielectric containing more nitrogen at the dielectric/Si interface or/and less bulk nitrogen, which can be attributed to less interface strain/stress and bulk trap. Electrical characterization of high-k MOSFET was performed by charge-pumping and charge separation techniques. Some interesting results are quite different from those generally observed in SiO: MOSFETs.

Chemical dry cleaning and pretreatment on the electrical and reliability characteristic of high-k gate dielectrics in MOS device

Effect of chemical dry cleaning (CDC) and pre-treatment (NH3 annealing) on the interface property of high-K gate dielectrics (NiTiO3) in MOS device have been investigated. A surface layer is damaged due to oxide dry etching (CHF3/CF4/Ar) process in active region formation. This damaged layer was generally removed by wet etching (HF) however it creates a rough layer on the substrate surface. It appears that the surface roughness by plasma dry etching is better then that by HF wet oxide etching. When the metal is directly deposited on the silicon substrate, a poor interface quality leads to a high leakage current. A damage-free, smooth surface, and thin interfacial layer formed on substrate surface are important for high-k gate dielectric process. Therefore, a method using Chemical Dry Cleaning (CF4/O2) is adopted after dry oxide etching (CHF3/CF4/Ar). In addition, CDC can then be adopted to effectively remove fluorocarbon residue and Si-F and Si-C bonds on the silicon surface etched in fluorocarbon plasma chemistry. After CDC, pre-deposition treatment can be employed to inhibit the growth of the interfacial layer. The pre-treatment strategies (NH3 annealing) are used to prevent silicide formation and to elevate the interface property of the devices. Finally, post deposition annealing (N2 annealing) can be performed to reduce the leakage current. These approaches not only strengthen the structure of Si-N bonds, but also improve the smoothness and uniformity at the interface of the metal oxide/silicon substrate.