Ping-Hung Tsai

Charge-Trapping-Type Flash Memory Device With Stacked High-

Operating properties of charge-trapping-type Flash memory devices with single or stacked structures on trapping layer are investigated in this letter. Improved operation and reliability characteristics can be achieved by adapting the stacked high-k films as charge-trapping layer due to the modification in the trap density and the energy level of traps, the mechanism of electron/hole transmission, and the suitable band offset. Moreover, with a small bandgap of second film in the stacked trapping layer, operating characteristics of devices are further enhanced.

k

Satisfactory operation and reliability characteristics of SONOS-type flash devices are achieved by an optimal Hf/Al content in HfAlO charge-trapping layer. Results indicate that operation performance can be improved by a suitable band offset of HfAlO charge-trapping layer. High-speed operation can be realized by adopting CHEI programming and F-N erasing for NOR flash applications.

Charge-Trapping Layer

Operation properties of polysilicon-oxide-nitride-oxide-silicon-type Flash device with HfAlO charge-trapping layer having various Al contents were investigated in this letter. Satisfactory performance in terms of operation speed, retention, and program/erase endurance of the Flash device is achieved with the optimal Al content of 18%-28% in the HfAlO trapping layer. In addition, high-speed operation can be attained with the combination of channel-hot-electron-injection programming and band-to-band hot hole erasing for NOR architecture applications.

Novel SONOS-Type Nonvolatile Memory Device with Suitable Band Offset in HfAlO Charge-Trapping Layer

Charge-pumping (CP) technique is proposed to simultaneously measure the border traps and interface-trap density (Dit). The charge pumped per cycle (Qcp) versus high level (Vh ) of gate pulse for various frequencies was used to observe the behavior of the bulk traps close to the interface as a function of the CP frequency. Evolution on Qcp as a function of frequency was successfully used to determine the depth profile of border-trap density near the high-kappa gate dielectric/Si interface. The influence of border trap in high-kappa dielectric on the Dit measurement can be prevented by an appropriate selection of gate frequency in CP technique

Novel SONOS-Type Nonvolatile Memory Device With Optimal Al Doping in HfAlO Charge-Trapping Layer

A novel charge-pumping (CP) technique is demonstrated to extract border-trap distribution for high- kappa gated MOSFETs. The varying-frequency CP method is shown to be more effective than the varying-amplitude one for probing border traps and extending the tunneling depth. A linear relationship of the Qcp versus ln(T rTf)1/2 plot can only be maintained at the CP frequency of 1 MHz, while not below 1 MHz, due to the influence of border traps near HfOxNy/Si interface. The proposed technique, which takes into consideration the effect of carrier tunneling in slow oxide traps, is used successfully to obtain the spatial and energy dependence of bulk trap density in high-kappa bulk

Depth Profiling of Border Traps in MOSFET With High-

The effects of nitrogen composition in HfxTayN metal-gate electrodes and postmetal annealing (PMA) treatment on the electrical properties of metal-oxide-semiconductor (MOS) devices were investigated in this work. The work function of HfxTayN gate electrodes can be adjusted by incorporating various nitrogen contents. It is found that the HfxTayN metal gate with higher nitrogen content can achieve better electrical characteristics in terms of leakage current and reliability while with only a slight increase in equivalent-oxide-thickness value. The face that only slight variation on electrical characteristics of MOS device with HfxTayN gate electrodes is observed after various PMA temperatures designates the excellent thermal stability of HfxTayN gate electrodes. The present study indicates that HfxTayN is a promising metal-gate-electrode material for advanced MOS devices.

kappa

The nanoparticles (NPs) have been widely used to supersede the conventional charge trapping layers (CTLs) of the silicon-oxide-nitride-oxide-silicon devices for reducing the charge loss due to a local leakage path. Moreover, to reduce the gate tunneling leakage current, the high-dielectric-constant (high-k) gate oxides with the identical equivalent-oxide thickness (EOT) are promising for the advanced metal-oxide-semiconductor (MOS) devices applications. Therefore, the NPs embedded in the high-k gate dielectric would be an attractive technology option for the nonvolatile memory device (NVM) applications.

Gate Dielectric by Charge-Pumping Technique

The high-kappa Hf-based charge trapping layer with Al₂O₃ blocking oxide in metal/Al₂O₃/HfO₂/SiO₂/silicon (MAHOS) structure is proposed. The Al2O3 as a blocking oxide on high-kappa HfO₂ and HfAlO charge trapping layers can improve the program/erase speed and has good retention characteristics, indicating that the MAHOS structure is a promising candidate for future high-speed flash memory. The charge trapping characteristics with different metal gates are also investigated

Detection of Border Trap Density and Energy Distribution Along the Gate Dielectric Bulk of High-

treatment using plasma immersion ion implantation (PIII) Kuei-Shu Chang-Liao*, Ping-Hung Tsai, H.Y. Kao, T.K. Wang, S.F. Huang, W.F. Tsai, and C.F. Ai Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C. Physics Division, Institution of Nuclear Energy Research, Taoyuan, Taiwan, R.O.C. *TEL: (886)-(3)-5742674, FAX: (886)-(3)-5720724, E-mail: Lkschang@ess.nthu.edu.tw