Chun-Yuan Lu

Depth Profiling of Border Traps in MOSFET With High-

Charge-pumping (CP) technique is proposed to simultaneously measure the border traps and interface-trap density (Dit). The charge pumped per cycle (Qcp) versus high level (Vh ) of gate pulse for various frequencies was used to observe the behavior of the bulk traps close to the interface as a function of the CP frequency. Evolution on Qcp as a function of frequency was successfully used to determine the depth profile of border-trap density near the high-kappa gate dielectric/Si interface. The influence of border trap in high-kappa dielectric on the Dit measurement can be prevented by an appropriate selection of gate frequency in CP technique

kappa

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.

Gate Dielectric by Charge-Pumping Technique

A novel p-channel flash device with a SiGe layer is proposed, which is based on the analysis made with the simulator MEDICI, to enhance the band-to-band-tunneling current and improve the programming speed. The programming biases of the p-channel flash device can be reduced with an equal programming speed. Simulation results show that more than one hundred times enhancement in the programming speed or 35% reduction of the drain voltage can be achieved in the proposed p-channel flash device with a 40% Ge content in the surface SiGe layer. In addition, a Si-cap layer is inserted between the SiGe and the tunneling oxide to obtain a high-quality interface and to optimize the cell structure

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

A novel charge-pumping (CP) technique is demonstrated to extract border-trap distribution for high- kappa gated MOSFETs. The varying-frequency CP method is shown to be more effective than the varying-amplitude one for probing border traps and extending the tunneling depth. A linear relationship of the Qcp versus ln(T rTf)1/2 plot can only be maintained at the CP frequency of 1 MHz, while not below 1 MHz, due to the influence of border traps near HfOxNy/Si interface. The proposed technique, which takes into consideration the effect of carrier tunneling in slow oxide traps, is used successfully to obtain the spatial and energy dependence of bulk trap density in high-kappa bulk

Enhanced Band-to-Band-Tunneling-Induced Hot-Electron Injection in p-Channel Flash by Band-gap Offset Modification

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high-k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high-k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO2-dominated high-k gate dielectrics is like mobile defect; while that with SiO2-dominated ones is similar to the near-interface/border trap.

Detection of Border Trap Density and Energy Distribution Along the Gate Dielectric Bulk of High-

Micro-scale droplet was effectively applied to the CPU cooling. The PZT actuated porous membrane device which generating the micro-scale droplet with high latent heat of phase changes between liquid and vapor of water to achieve high heat transfer performance, it could remove heat from the CPU surface effectively for over 100 Watts as cooling system. And the device operating below the pressure of ambient environment prevents leakage as system fail. In order to design an efficient cooling device, it was important to study the dimensional effects of PZT actuator on the orifice plate vibration mode to pinch off droplet. The frequency and the applied voltage used to energize the PZT transducer were also important parameters that should be properly controlled in order to achieve the optimal liquid breakup conditions. The maximum flow rate approach 27 ml/min when operated at 50 kHz with 2.75 W, It also reveals the low noise and power consumption in the CPU cooling system

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For better understanding the hot-carrier-induced reliability problems, a charge-pumping technique has been developed to profile the Q/sub ot/ and N/sub it/ directly from the experimental results. However, the key neutralization condition is acquired by trial and error, which takes much time and effort. Therefore, a technique of two-step neutralization is proposed to find out the appropriate neutralization condition in this work. This two-step neutralization combined with the error-reduction method is shown to carry out the profiling more quickly and precisely.

Gated MOS Devices

A number of new device structures have been reported recently to improve the operation performance of flash memory. In this work, a novel flash device with a vertical dielectric layer in the depletion region is proposed through simulation approach. The simulation results show that the employment of a vertical dielectric layer in the depletion region can improve the operation performance of flash memory. The improvement can be attributed to a lower potential in the central region of device channel and the increase of the potential drop in the channel direction near drain junction. Thus, this proposed vertical dielectric layer increases the electrical field of the channel and thus the probability and the momentum of electron injection. The operation characteristics of the flash device with a vertical dielectric layer in the depletion region of source and drain are superior to those without. In addition, it is found that a vertical dielectric layer with lower dielectric constant can enhance the operation performance of flash device even more.

Tunneling component suppression in charge pumping measurement and reliability study for high-k gated MOSFETs

The lateral profile of oxide trap charge (Q/sub ot/) and interface traps (N/sub it/) is crucial for improving the reliability of MOSFET and flash memory device. A charge pumping technique has been shown to profile the Q/sub ot/ and N/sub it/ directly from the experimental results. However, the neutralization condition is acquired by trial and error, which takes much time and effort. Therefore, a technique of two-step neutralization is proposed to find out the appropriate neutralization condition in this work, which is effectively applied to this profiling technique to various dimension and structures of devices. This two-step neutralization combined with the error-reduction method is expected to profile Q/sub ot/ and N/sub it/ more quickly and precisely.

4A-3 Traveling Wave Driven Micro-Dispenser for CPU Cooling Application

High-k material has been proposed to replace the conventional silicon dioxide (SiO2) as gate dielectrics of MOS devices. However, the quantity and extent of charge trapping in the high-k dielectric strongly affect the electrical characteristics of high-k gated MOS devices. Charge pumping (CP) technique is well known to be a very efficient tool to study the interface traps and border traps of MOS devices with high-k gate dielectrics. Yet, the gate leakage current is the main problem as the CP technique is applied to measure a thin high-k gated MOS device. In this work, a simple method is proposed to separate the CP current from the parasitic tunneling component in MOS devices with thin high-k gate dielectric.