Chin-Miin Shyu

Mismatch drift: a reliability issue for analog MOS circuits

Mismatch drift is a major process reliability issue for analog and mixed-signal designs. Mismatch stability was examined for a 0.8- mu m CMOS process using a cascode current minor test circuit. After 1000-h burn-in at 125 degrees C under matched gate voltage stress, no drift in parameter matching was measured. However, for the same burn-in conditions with unmatched gate voltage stress, drifts in threshold voltage mismatch of 0.3 mV for n-channel and 2.4 mV for p-channel transistor pairs have been observed. This mismatch drift is larger for short-channel devices, indicating that the drift-causing phenomenon is greater at the drain/source edge.<<ETX>>

A CMOS process for mixed mode signal design

In this paper we describe a modular approach to convert digital CMOS process for mixed-signal CMOS applications by incorporating LATID NMOSFET, HALO PMOSFET, and poly-to-substrate capacitors. Significant improvements in analog performance are achieved without degrading digital device characteristics.