Christopher Michael

Statistical modeling of device mismatch for analog MOS integrated circuits

A generalized parameter-level statistical model, called statistical MOS (SMOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics is described. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area. Using a Monte Carlo approach to parameter sampling, circuit output means and standard deviations can be simulated. Incorporated in a CAD environment, these modeling algorithms will provide the analog circuit designer with a method to determine the effect of both circuit layout and device sizing on circuit output variance. Test chips have been fabricated from two different fabrication processes to extract statistical information required by the model. Experimental and simulation results for two analog subcircuits are compared to verify the statistical modeling algorithms. >

Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits

List of Figures. List of Tables. Preface. 1. Introduction. 2. Survey of Statistical Modeling and Simulation Techniques. 3. Statistical MOS Model. 4. Experimental Process Characterization for MOS Statistical Model. 5. CAD Implementation of the SMOS Model. 6. Statistical CAD of Analog MOS Circuits. 7. Applications of the SMOS Model to Digital Integrated Circuits. 8. Conclusion and Future Work. Appendix A: MCP-SPICE Implementation of SMOS. Appendix B: APLAC Input Files. Bibliography. Index.

Characterization of transistor mismatch for statistical CAD of submicron CMOS analog circuits

The use of a four-parameter MOS model to characterize drain current mismatch is discussed. Guidelines for the accurate and repeatable measurement of transistor parameter mismatch are presented, along with two extraction methodologies based upon these guidelines. Parameter mismatch measurements made on 430 NMOS and 430 PMOS transistor pairs fabricated in a 0.8-/spl mu/m process are used to predict the drain current mismatch of the same population of transistors. Comparisons are made between the predicted and measured values.<<ETX>>

A flexible statistical model for CAD of submicrometer analog CMOS integrated circuits

A new statistical MOS model has been developed for computer-aided design of submicrometer analog integrated circuits. This model accounts for both parameter mismatch and inter-die parameter variations, both of which contribute to statistical variations in analog circuit performance. New characterization methods were developed to improve model fit to parameter standard deviations over a broad range of transistor biases. Implementation of this model in HSPICE is demonstrated, meaning that no exotic simulation tools are required to perform the statistical simulations. The model was tested on a 0.8 /spl mu/m CMOS process, with simulated and measured values of drain current variability showing excellent agreement.

Statistical constrained optimization of analog MOS circuits using empirical performance models

In this paper, we present a statistical constrained CAD-compatible optimization algorithm for analog MOS integrated circuit design. The algorithm uses design of experiments (DOE), together with the response surface methodology (RSM), to determine simple empirical models relating circuit performances to device sizes. It then applies the Lagrange multiplier method to solve the resulting statistical constrained nonlinear optimization problem. The algorithm is guaranteed to converge to the global minimum. Using this new algorithm, we show that the transistors which cause variations in the performances of a two-stage op-amp can be identified and resized in an area-efficient manner to meet performance specifications.<<ETX>>

Statistical techniques for the computer-aided optimization of analog integrated circuit

A CAD tool capable of performing statistical circuit simulation, design, and optimization is described. The core of this tool is a general, CAD-compatible, statistical model which accounts for the effect of device area, transistor bias, and circuit layout on the variation of MOS integrated circuits. The statistical model has been incorporated into an object-oriented circuit simulator, APLAC, which has sufficient flexibility to allow optimization loops within a simulation input deck. The optimization of a two-stage operational amplifier, including the optimization of the standard deviation of the offset voltage, is performed using both steepest descent and constrained optimization techniques as an illustration of this statistical CAD tool. In this example, it is shown that the transistors which cause variations in op-amp circuit performance can be identified and resized in an area-efficient manner to meet a prescribed parametric circuit yield.

Yield optimization of analog MOS integrated circuits including transistor mismatch

With the aid of the SMOS (statistical MOS) model, it is presently possible to simulate random device mismatch effects on the circuit performance. Two different optimization algorithms, which, together with the SMOS model, can create an efficient CAD environment for integrated circuit designers are presented. The goal of these optimizations is for the user to determine the optimal circuit modifications in order to achieve a user specified parametric yield, as well as the nominal circuit specifications. The optimization algorithms use the steepest descent method and the experiment design method with response surface methodology (RSM). Area optimization of a Miller compensated operational amplifier is used as an example.<<ETX>>

Mismatch drift: a reliability issue for analog MOS circuits

Mismatch drift is a major process reliability issue for analog and mixed-signal designs. Mismatch stability was examined for a 0.8- mu m CMOS process using a cascode current minor test circuit. After 1000-h burn-in at 125 degrees C under matched gate voltage stress, no drift in parameter matching was measured. However, for the same burn-in conditions with unmatched gate voltage stress, drifts in threshold voltage mismatch of 0.3 mV for n-channel and 2.4 mV for p-channel transistor pairs have been observed. This mismatch drift is larger for short-channel devices, indicating that the drift-causing phenomenon is greater at the drain/source edge.<<ETX>>

Survey of Statistical Modeling and Simulation Techniques

The backbone of all statistical circuit analyses is a computer-aided design (CAD) tool capable of performing simulations based on an accurate statistical device model. This statistical device model must comprehend the effect of parameters, such as device geometries and circuit layout, under the control of the circuit designer. Furthermore, due to the number of circuit simulations required to perform statistical simulations, generally Monte Carlo techniques are employed, the statistical model must be incorporated into a circuit simulation package. Meeting all the aforementioned requirements for statistical modeling and simulation is a difficult task.

Worst case analysis of low-voltage analog MOS integrated circuits

A methodology for worst case analysis of low voltage analog MOS integrated circuits is presented. It relates parameter to current mismatch in a transistor pair analytically and the current mismatch is regarded as a random variable. It is shown that the algorithm is efficient and is readily extended to the circuit level. The effect of the active area of critical transistor pairs is also investigated. The methodology is used to study the DC offset in low voltage CMOS op amps.