Chih Sieh Teng

A flexible statistical model for CAD of submicrometer analog CMOS integrated circuits

A new statistical MOS model has been developed for computer-aided design of submicrometer analog integrated circuits. This model accounts for both parameter mismatch and inter-die parameter variations, both of which contribute to statistical variations in analog circuit performance. New characterization methods were developed to improve model fit to parameter standard deviations over a broad range of transistor biases. Implementation of this model in HSPICE is demonstrated, meaning that no exotic simulation tools are required to perform the statistical simulations. The model was tested on a 0.8 /spl mu/m CMOS process, with simulated and measured values of drain current variability showing excellent agreement.

Mismatch drift: a reliability issue for analog MOS circuits

Mismatch drift is a major process reliability issue for analog and mixed-signal designs. Mismatch stability was examined for a 0.8- mu m CMOS process using a cascode current minor test circuit. After 1000-h burn-in at 125 degrees C under matched gate voltage stress, no drift in parameter matching was measured. However, for the same burn-in conditions with unmatched gate voltage stress, drifts in threshold voltage mismatch of 0.3 mV for n-channel and 2.4 mV for p-channel transistor pairs have been observed. This mismatch drift is larger for short-channel devices, indicating that the drift-causing phenomenon is greater at the drain/source edge.<<ETX>>

Submicron Large-Angle-Tilt Implanted Drain technology for mixed-signal applications

This paper reports the use of LATID in submicron MOS technology to improve both analog and digital device performance and reliability. It is demonstrated that LATID technology not only improves device reliability, but also significantly improves output resistance and voltage gain. A submicron CMOS technology optimized for mixed-signal applications based on a conventional CMOS process has been fabricated without compromising digital performance or increasing process complexity.<<ETX>>

Analog characteristics of drain engineered submicron MOSFETs for mixed-signal applications

Abstract Drain engineered MOSFETs are compared in terms of their impact on analog performance for submicron mixed-signal applications. The high energy implanted lightly doped drain (LDD) devices are shown only to improve voltage gain at high drain voltage, while large-angle-tilt implanted drain (LATID) devices show that the reduced substrate current and junction depth due to the tilt angle implant can significantly improve maximum available gain and voltage swing. Also, superior analog hot-carrier immunity in LATID MOSFETs is demonstrated through offset voltage drift in source-coupled transistor pair. These results suggest that LATID technology is promising for applications to submicron mixed analog/digital circuits.

A CMOS process for mixed mode signal design

In this paper we describe a modular approach to convert digital CMOS process for mixed-signal CMOS applications by incorporating LATID NMOSFET, HALO PMOSFET, and poly-to-substrate capacitors. Significant improvements in analog performance are achieved without degrading digital device characteristics.

Reliability Issues with Mixed-Signal CMOS Technology

In a Mixed-Signal IC, both digital and analog circuits exist on the same chip. Analog circuit blocks require technology attributes like precise device matching, low parametric drifts and low noise. These requirements raise additional reliability issues, over and above the reliability concerns associated with digital circuits. CMOS device reliability for mixed-signal technologies can be enhanced by modifying device architecture and improving gate oxide integrity. Interconnect metallurgy plays an important role in determining electromigration related contact/via resistance change which may impact matching of devices and resistor pairs. Appropriate source/drain engineering, device design and utilizing nitrided gate oxide has been shown to produce extremely stable devices. This article will cover process architecture and material issues related with device stability and interconnect metallurgy issues related with contact/via stability, especially with W-Plugs.