Kuan-Neng Chen

Demonstration and Electrical Performance of Cu–Cu Bonding at 150 °C With Pd Passivation

In this paper, one low-temperature direct Cu bonding structure is demonstrated using metal passivated layers. With the protection of Cu bonding layer, the bonding temperature can be reduced to meet low thermal budget requirement. Direct wafer-level Cu bond scheme with Pd passivation is successfully demonstrated at 150°C. Electrical performance along with the material analysis and reliability tests of passivated Cu bonded structures is presented. Furthermore, reliability assessments, including current stressing, temperature cycling, and unbiased highly accelerated stress test, imply excellent stability without electrical degradation. Diffusion behavior between passivation Pd and Cu layers is surveyed, and the corresponding mechanism is discussed as well. The low-temperature Cu/Pd-Pd/Cu bonded structure presents good bond quality and electrical performance, indicating a great potential for 3-D integration applications.

Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding

We demonstrate a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding. Hybrid Cu-oxide hybrid bonding shows excellent bond quality and performances in terms of alignment, bond strength, and ambient permeation oxidation. Excellent performances of initial reliability and quality evaluations for Cu-oxide hybrid bonding are key milestones in proving manufacturability of 3D integration technology.

Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV)

Abstract3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.

Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies include TSV fabrication, micro-bumping, hybrid scheme making, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. 5μm TSV, 10μm micro-bump, 20μm pitch, 40μm thin wafer, and 250°C low temperature W2W hybrid bonding have been successfully integrated in the integration platform. The 3D scheme was characterized and assessed to have excellent electrical performance and reliability, and is potentially to be applied for 3D product applications.

An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes

Highly integrated neural sensing microsystems are crucial to capture accurate signals for brain function investigations. In this paper, a 256-channel/25 mm2 neural sensing microsystem is presented based on through-silicon-via (TSV) 2.5D integration. This microsystem composes of dissolvable μ-needles, TSV-embedded μ-probes, 256-channel neural amplifiers, 11-bit area-power-efficient SAR ADCs and serializers. Based on the dissolvable μ-needles and TSV 2.5D integration, this microsystem can detect 256 ECoG/LFP signals within the small area of 5mm × 5mm. Additionally, the neural amplifier realizes 57.8dB gain with only 9.8μW for each channel, and the 9.7-bit ENOB of the SAR ADC at 32kS/s can be achieved with 0.42μW and 0.036 mm2. The overall power of this microsystem is only 3.79mW for 256-channel neural sensing.

Ultrathin glass wafer lamination and laser debonding to enable glass interposer fabrication

Interposer fabrication processes are applied in three-dimensional (3-D) integrated circuit (IC) integration to shorten the interconnection among different stacked chips and substrates. Because Si is a common material in semiconductor technology, Si interposers have been widely studied in many research activities. Compared with a Si wafer, glass substrates have the advantages of high resistivity, low dielectric constant, low insertion loss, adjustable coefficient of thermal expansion (CTE), and the possibility to use panel-size substrates as well as thin glass substrates (100 μm) to avoid the costly thinning process for realization of low-cost 2.5-D ICs. Thus, glass interposer fabrication is studied thoroughly in this paper. Thin glass wafers have reduced mechanical stiffness. Therefore, handling and shipping thin glass wafers (≤100 μm) throughout the semiconductor fabrication and packaging assembly processes are critical. Temporary wafer bonding technology is used in this study to bond a thin glass wafer to a carrier to improve the rigidity. Vacuum lamination technology is used in this study as a bonding process to enhance the costeffectiveness. After processing, the carrier is removed by laser debonding. The thin glass wafer with structures on both sides does not need to undergo a glass thinning process and saves a lot of cost compared to the traditional glass or Si interposer processes. Thin 300-mm glass wafers 100 μm thick are evaluated as: (a) blank thin glass wafers and (b) thin glass wafers with through-glass vias (TGVs) 30 μm in diameter. A UV laser with a wavelength of 308 nm, which has the benefit of less impact to the device, was adopted to laser debonding. This method also has several benefits such as high throughput, low temperature, zero-force debonding, and possible selective laser debonding. Adhesive and release layers are key enabling materials for thin glass handling. In addition, the use of a laminator for temporary bonding and laser debonding are included in this study. Based on the excellent fabrication, the thin glass interposer has great potential to be applied in 2.5-D integration applications.

Study of a Novel Amorphous Silicon Temporary Bonding and Corresponding Laser Assisted De-bonding Technology

A novel amorphous silicon temporary bonding and corresponding laser assisted de-bonding technology are investigated for the improvement of 3D integration. Excellent bonding results with real device wafer with α-IGZO thin-film transistor are shown at the bonding temperature of 210°C, as well as outstanding performances for bonding strength, thermal stability, reliability and chemical resistance. Laser ablated amorphous silicon is proved stable and ultra-fast. Advantages of excellent bonding quality, lower cost and higher throughput demonstrate that this scheme can be a potential candidate in 3D integration platform.

A Novel Flexible 3-D Heterogeneous Integration Scheme Using Electroless Plating on Chips With Advanced Technology Node

A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node.

Quartz resonator assembling with TSV interposer using polymer sealing or metal bonding

This paper presents one wafer level packaging approach of quartz resonator based on through-silicon via (TSV) interposer with metal or polymer bonding sealing of frequency components. The proposed silicon-based package of quartz resonator adopts several three-dimensional (3D) core technologies, such as Cu TSVs, sealing bonding, and wafer thinning. It is different from conventional quartz resonator using ceramic-based package. With evaluation of mechanical structure design and package performances, this quartz resonator with advanced silicon-based package shows great manufacturability and excellent performance to replace traditional metal lid with ceramic-based interposer fabrication approach.

Multi-layer adaptive power management architecture for TSV 3DIC applications

In this work, a multi-layer hierarchical distributed power delivery architecture for TSV 3DIC is proposed. By decoupling global and local power networks, the proposed power delivery architecture can be flexibly configured for different power requests. The decoupled power architectures can also greatly reduce the required decoupling capacitor sizes for voltage stabilization. Meanwhile, a multi-threshold CMOS switched capacitor DC-DC converter with up to 78% power efficiency is implemented in 65nm CMOS for hierarchical distributed power delivery architecture. An adaptive power management technique is presented to work in the local power network to increase the power efficiency. The proposed multi-layer hierarchical distributed power delivery architecture is also very useful for the heterogeneous integration in 3DIC chips.