Ching-Yuh Tsay

Error correction techniques for high-performance differential A/D converters

Error correction techniques that overcome several error mechanism that can affect the accuracy of charge-redistribution analog-to-digital converters (ADCs) are described. A correction circuit and a self-calibration algorithm are used to improve the common-mode rejection of the differential ADC. A modified technique is used to self-calibrate the capacitor ratio errors and obtain higher linearity. The residual error of the ADC due to capacitor voltage dependence is minimized using a quadratic voltage coefficient (QVC) self-calibration scheme. A dual-comparator topology with digital error correction circuitry is used to avoid errors due to comparator threshold hysteresis. A fully differential charge-redistribution ADC implemented with these techniques was fabricated in a 5-V 1- mu m CMOS process using metal-to-polysilicide capacitors. The successive-approximation converter achieves 16-b accuracy with more than 90 dB of common-mode rejection while converting at a 200-kHz rate. >

Codec for echo-canceling, full-rate ADSL modems

A codec, fabricated in 3.3 V CMOS, provides the low-voltage transmitter and receiver interfaces between DSP and high voltage hybrid circuit for either the central office (CO) or the remote terminal (RT), configurable by metal mask option. The die area is 67.5 square millimeters. The power dissipation is 600 mW (CO) and 760 mW (RT).