Richard K. Hester

Design considerations for high-frequency continuous-time filters and implementation of an antialiasing filter for digital video

An approach that has made possible the integration of video frequency continuous-time filters with wide dynamic range is discussed. The tuning scheme necessary to maintain the stable and accurate frequency response in the presence of temperature variations, process tolerance, and aging is described. Detailed design techniques specific to high-frequency operation are introduced to implement a 5-V, seventh-order elliptic analog magnitude filter for antialiasing in digital video applications. The filter, based on a G/sub m/-C technique, exhibits a dynamic range of 61 dB and dissipates a power of 75 mW. Ninety-two chips from various wafers and two different process runs were tested. Seventy-five percent of the fabricated chips were functional, and 63% of them met the commercial-grade specifications in spite of an error in the layout which forced the phase control circuitry to perform suboptimally. >

Error correction techniques for high-performance differential A/D converters

Error correction techniques that overcome several error mechanism that can affect the accuracy of charge-redistribution analog-to-digital converters (ADCs) are described. A correction circuit and a self-calibration algorithm are used to improve the common-mode rejection of the differential ADC. A modified technique is used to self-calibrate the capacitor ratio errors and obtain higher linearity. The residual error of the ADC due to capacitor voltage dependence is minimized using a quadratic voltage coefficient (QVC) self-calibration scheme. A dual-comparator topology with digital error correction circuitry is used to avoid errors due to comparator threshold hysteresis. A fully differential charge-redistribution ADC implemented with these techniques was fabricated in a 5-V 1- mu m CMOS process using metal-to-polysilicide capacitors. The successive-approximation converter achieves 16-b accuracy with more than 90 dB of common-mode rejection while converting at a 200-kHz rate. >

Fully differential ADC with rail-to-rail common-mode range and nonlinear capacitor compensation

One of the sources of nonlinearity in charge redistribution analog-to-digital converters (ADCs) is capacitor voltage dependence. While it is possible to address this problem through capacitor fabrication technology improvements, situations arise where it is more desirable to use circuit techniques. The conventional fully differential charge redistribution converter topology eliminates errors proportional to the capacitor linear voltage coefficient, but its comparator is subjected to the common-mode input signal. When converting unbalanced differential signals, linearity is achieved only with large comparator common-mode rejection. An alternative differential converter topology that isolates the comparator from the input common-mode signal, resulting in a common-mode rejection ratio of -73 dB, is presented. In addition, a circuit that cancels the error caused by the quadratic capacitor voltage coefficient is described. Measurements show that it is capable of increasing the converter linearity by an order of magnitude. >

High efficiency wide load range buck/boost/bridge photovoltaic microconverter

Series strings of photovoltaic modules with integrated dc-dc microconverters can harvest more energy compared to conventional string-inverter architectures if the arrays are partially shaded or the modules mismatched. This work presents a multi-mode dc-dc converter as a candidate microconverter topology for photovoltaic modules. The topology constitutes a single inductor and four switching devices and can function in either buck, boost or an intermediate bridge mode based on the load. The proposed maximum power point tracking scheme is capable of tracking the true maximum even in partially-shaded PV modules. An experimental prototype demonstrates efficiency above 95 % at 215 W over a load range of 3 A to 7 A.

A low-power 12-b analog-to-digital converter with on-chip precision trimming

The design and performance of a 12-b charge redistribution analog-to-digital converter (ADC) is described. The architecture is chosen to minimize power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a 1- mu m CMOS process. It converts at a 200-kHz rate with a power dissipation of 10 mW. >

Codec for echo-canceling, full-rate ADSL modems

A codec, fabricated in 3.3 V CMOS, provides the low-voltage transmitter and receiver interfaces between DSP and high voltage hybrid circuit for either the central office (CO) or the remote terminal (RT), configurable by metal mask option. The die area is 67.5 square millimeters. The power dissipation is 600 mW (CO) and 760 mW (RT).

A 5 V 7th-order elliptic analog filter for digital video applications

For high-frequency performance, seventh-order elliptic response was implemented using the GmC topology. Feedforward-feedback paths for transmission zeros were implemented by connecting capacitors between the appropriate nodes on the basis of signal flow-graph analysis. For dynamic range optimization, only integral scaling of Gm was performed using multiple transconductance amplifiers. To facilitate signal addition, each Gm block is a two-input stage, single-output-stage transconductance amplifier. Monte Carlo simulation indicates that the element matching achievable in fabrication meets specifications, provided the nominal cutoff frequency of the master is maintained by an on-chip tuning system. Simulations show that, to achieve this, it is necessary to tune both the magnitude and the phase of the filter. The master-slave approach of tuning used maintains accuracy in the presence of fabrication tolerances, temperature variations, and aging. The complete filter was implemented in a 1- mu m N-well CMOS process. The active area is 6 mm/sup 2/. The measured frequency response and the output noise spectrum are shown. To assess viability of this scheme in video antialiasing applications, 92 chips from various wafers were tested for yield, the variability of cutoff frequency, and ripple amplitude. The yield was 47%.<<ETX>>

A 20 W/Channel Class-D Amplifier With Near-Zero Common-Mode Radiated Emissions

A class-D amplifier that employs a new modulation scheme and associated output stage to achieve true filter-less operation is presented. It uses a new type of BD modulation that keeps the output common-mode constant, thereby removing a major contributor to radiated emissions, typically an issue for class-D amplifiers. The amplifier meets the FCC class B standard for radiated emissions without any LC filtering. It can accomplish this without any degradation to audio performance and while retaining high efficiency. THD+N is 0.19% at 1 kHz while supplying 5 W to an 8 Ohm load from a 12 V supply. Efficiency is 90% while providing 10 W under the same supply and load conditions. The new output stage occupies 1.8 mm2 per channel using the high voltage devices of a 0.25 ¿m BCD process.

A 20W/channel Class-D amplifier with significantly reduced common-mode radiated emissions

Due to their rail-to-rail switching nature, Class-D audio amplifiers are prone to generating electromagnetic interference (EMI) that is in excess of what is acceptable in many systems. Such systems typically require devices to limit their EMI to an accepted standard, such as the FCC Class-B standard. In Class-D audio amplifiers that employ Class-BD modulation [1] using a single supply, the common-mode output signal, VCM, has a significant EMI component because this signal also swings rail-to-rail at the amplifier switching frequency, typically in the hundreds of kHz. This phenomenon is illustrated in the upper signals of Fig. 26.4.1.

An ADSL central office analog front-end integrating actively-terminated line driver, receiver and filters

The analog front-end (AFE) of a central office ADSL modem is typically partitioned into two technologies. The data converters, analog filters and sometimes receiver amplifier are fabricated on a 3.3 V or 5 V mixed signal CMOS, while the remainder employs a higher-voltage bipolar process. This circuit has alternative AFE partitioning where the analog filters and receiver amplifier are integrated with the line driver in a 15 V dielectrically-isolated bipolar technology.