Khen-Sang Tan

Design considerations for high-frequency continuous-time filters and implementation of an antialiasing filter for digital video

An approach that has made possible the integration of video frequency continuous-time filters with wide dynamic range is discussed. The tuning scheme necessary to maintain the stable and accurate frequency response in the presence of temperature variations, process tolerance, and aging is described. Detailed design techniques specific to high-frequency operation are introduced to implement a 5-V, seventh-order elliptic analog magnitude filter for antialiasing in digital video applications. The filter, based on a G/sub m/-C technique, exhibits a dynamic range of 61 dB and dissipates a power of 75 mW. Ninety-two chips from various wafers and two different process runs were tested. Seventy-five percent of the fabricated chips were functional, and 63% of them met the commercial-grade specifications in spite of an error in the layout which forced the phase control circuitry to perform suboptimally. >

Error correction techniques for high-performance differential A/D converters

Error correction techniques that overcome several error mechanism that can affect the accuracy of charge-redistribution analog-to-digital converters (ADCs) are described. A correction circuit and a self-calibration algorithm are used to improve the common-mode rejection of the differential ADC. A modified technique is used to self-calibrate the capacitor ratio errors and obtain higher linearity. The residual error of the ADC due to capacitor voltage dependence is minimized using a quadratic voltage coefficient (QVC) self-calibration scheme. A dual-comparator topology with digital error correction circuitry is used to avoid errors due to comparator threshold hysteresis. A fully differential charge-redistribution ADC implemented with these techniques was fabricated in a 5-V 1- mu m CMOS process using metal-to-polysilicide capacitors. The successive-approximation converter achieves 16-b accuracy with more than 90 dB of common-mode rejection while converting at a 200-kHz rate. >

Fully differential ADC with rail-to-rail common-mode range and nonlinear capacitor compensation

One of the sources of nonlinearity in charge redistribution analog-to-digital converters (ADCs) is capacitor voltage dependence. While it is possible to address this problem through capacitor fabrication technology improvements, situations arise where it is more desirable to use circuit techniques. The conventional fully differential charge redistribution converter topology eliminates errors proportional to the capacitor linear voltage coefficient, but its comparator is subjected to the common-mode input signal. When converting unbalanced differential signals, linearity is achieved only with large comparator common-mode rejection. An alternative differential converter topology that isolates the comparator from the input common-mode signal, resulting in a common-mode rejection ratio of -73 dB, is presented. In addition, a circuit that cancels the error caused by the quadratic capacitor voltage coefficient is described. Measurements show that it is capable of increasing the converter linearity by an order of magnitude. >

Polycide/metal capacitors for high precision A/D converters

The authors present a novel metal-to-silicide-polysilicon capacitor and compare it with metal-to-polysilicon capacitors and conventional polysilicon-to-polysilicon capacitors. Voltage coefficient data for these capacitor structures with oxide, oxide/nitride, oxide/nitride/oxide, and nitride dielectrics are also discussed. It is shown that when metal-to-silicided polysilicon capacitors are used, voltage coefficients of less than 4 p.p.m./V can be attained, which is considerably less than that obtained when metal-to-poly or conventional poly-to-poly capacitors are used. For high-precision A/D converters, this value will make possible accuracies of up to 18 bits through self-calibration.<<ETX>>

A 5 V 7th-order elliptic analog filter for digital video applications

For high-frequency performance, seventh-order elliptic response was implemented using the GmC topology. Feedforward-feedback paths for transmission zeros were implemented by connecting capacitors between the appropriate nodes on the basis of signal flow-graph analysis. For dynamic range optimization, only integral scaling of Gm was performed using multiple transconductance amplifiers. To facilitate signal addition, each Gm block is a two-input stage, single-output-stage transconductance amplifier. Monte Carlo simulation indicates that the element matching achievable in fabrication meets specifications, provided the nominal cutoff frequency of the master is maintained by an on-chip tuning system. Simulations show that, to achieve this, it is necessary to tune both the magnitude and the phase of the filter. The master-slave approach of tuning used maintains accuracy in the presence of fabrication tolerances, temperature variations, and aging. The complete filter was implemented in a 1- mu m N-well CMOS process. The active area is 6 mm/sup 2/. The measured frequency response and the output noise spectrum are shown. To assess viability of this scheme in video antialiasing applications, 92 chips from various wafers were tested for yield, the variability of cutoff frequency, and ripple amplitude. The yield was 47%.<<ETX>>

The effect of dielectric relaxation on charge-redistribution A/D converters

The authors examine the extent to which dielectric relaxation in typical monolithic capacitors degrades the performance of charge-redistribution analog-to-digital (A/D) converters. They present experimental device data from a monolithic capacitor test circuit, describe an empirical capacitor model fit to the measurements, and compare simulated A/D system errors with those observed in a monolithic, 10-b, 3.3-ms A/D converter. It is believed that these techniques for modeling and predicting A/D converter errors will play an important role in making appropriate technology decisions and in guiding system and circuit design of high-precision monolithic converters of the future

A 5 V, 16 b 10 mu s differential CMOS ADC

A fully differential charge redistribution analog-to-digital-converter (ADC) chip fabricated in a 5-V, 1.0- mu m CMOS process that includes polysilicide-to-metal capacitors, polysilicon resistors, and low-threshold n-channel transistors is discussed. The successive-approximation ADC uses self-calibration of capacitor, gain, and offset errors. Self-correction techniques are also used to eliminate first-order common-mode error and first- and second-order capacitor voltage dependence. A comparator topology minimizes comparator offset hysteresis.<<ETX>>

A low power 12 b analog-to-digital converter with on-chip precision trimming

The design and performance of a 12 b charge redistribution ADC is described. The architecture is chosen to minimize conversion time and power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a linear 1 mu m CMOS process. The die area, including the 12 b parallel digital interface is 15 kmil/sup 2/. The power dissipation is under 15 mW, making the energy per conversion only 45 nJ.<<ETX>>