Chock Hing Gan

Stress-induced leakage currents of CMOS ULSI devices with shallow trench isolation

The correlation of MOSFET electrical characteristics to the levels of mechanical stress in STI structures used for the device manufacturing has been analyzed. The model of stress evolution during STI formation was developed based on the results of experimental measurements and computer simulations. Accordingly, STI processes creating different levels of stresses were designed and used to manufacture ULSI. Electrical parameters of a large variety of MOSFET devices were tested and weighted against the STI processes employed. This enabled the identification of the device leakage currents which resulted from high STI stress: the diode leakage dependent on isolation width, MOSFET standby currents dependent on active device width and gate bias, and the excessive leakage of field-edge-intensive devices. The first phenomenon was found to be associated with the incident of dislocations. The other kinds of leakage could reach critical levels even at moderate stress below the threshold for the onset of dislocation. According to the results of the device leakage characterization, critical stress states of STI structures can be readily monitored using conventional approaches of electrical testing. This provides an effective means for STI process and material integration and obtaining low stress dislocation-free structures.

Nitrogen implantation: reverse short channel effects improvement and its drawbacks

In this paper, the effects of implanting nitrogen ions (N+) into the channel and source/drain/poly-silicon gate (poly-Si) regions on transistor characteristics are investigated. It was found that the use of N+ implantation into the channel reduces the reverse short channel effects (RSCE) tremendously. However, threshold voltage shifts of both n-ch an p-ch devices were observed. The thinning of the field oxide due to the extra N+ implantation was also seen. We attribute these threshold voltage shifts to the partial activation of the implanted nitrogen ions. When N+ were implanted into the source/drain/poly-Si regions, it was found that the roll-off of the n-ch devices and p+/n-well junction leakage current was degraded. We propose that these are due to the thinning of the field oxide at the birds beak and to the partial activation of the implanted N+. It was found that there was no degradation in the n+/p-well junction leakage current which is consistent with the proposed mechanism.

Comprehensive study of indium-implantation-induced damages in 0.25-um MOSFETs

In this paper, an investigation of the DC characteristics of 0.25 micrometers indium-implanted MOSFETs concerning on indium implantation induced damages is presented. The experimental data indicates that the devices with indium-implanted channel tend to show increases in device leakage current, which could be attributed the indium implantation induced damages. The impact of the indium implantation on the degradation of device performance was investigated through detailed studies of device I-V characteristics, and the measurement results are found to correlate well with the variations in the process conditions. Our findings indicate that the elimination of the implantation-induced damages by post implantation annealing is particularly important for deep sub-micron MOSFETs using indium implantation.

Impact of boron penetration on gate oxide reliability and device performance in a dual-gate oxide process

The effect of boron penetration on device performance and gate oxide reliability of P+ polysilicon gate MOSFET of a dual oxide process with salicide block module was investigated. To get stable non-salicided poly sheet resistance, a capping oxide is required before source/drain RTA anneal. It is found that the transistor performance and gate oxide reliability were degraded with the capping oxide. The optimization scheme by replacing BF2 with Boron for P+ implant is demonstrated.

Analysis of N-channel transistor punch-through related to STI process

In this paper we study the causes of an unusually high N- channel transistor punch through leakage using a shallow trench isolation process. This resistive short between source and drain exhibits high structural dependence and has a strong dependence on the channel length and the total field edge of the device. Unlike the normal off-channel leakage. The leakage current of this resistive short shows weak dependence on temperature. Such a correlation between leakage and structure is examined for the first time in this paper. Experimentation with various trench liner oxidation schemes and gap-fill densification was the key to resolve the leakage.