Ravi Sundaresan

Void formation in titanium desilicide/p+ silicon interface: impact on junction leakage and silicide sheet resistance

We have observed the formation of voids at the interface of TiSi 2 /p + -Si after the titanium-salicidation process in a deep-sub-micron CMOS technology. In our study, most of the voids occurred at the intersection of the polycrystalline TiSi 2 grain boundary with the p + Si substrate and had an extended defect into the p + Si substrate. In some cases, for voids that were not located at the TiSi 2 grain boundary, the substrate defects extended from the void/p + -Si interface into the silicide film, resulting in micro-twin defects. In addition, discrete and isolated defects were found at the birds beak tips, which are most likely due to dislocation loops. However, its density was very low. Our investigation shows that void formation is relatively sensitive to the BF 2 + implant and p + junction annealing temperature, and can be completely avoided by subjecting the p + junctions to a high temperature anneal at 850°C for 45 min prior to the salicidation process. We attribute these voids to the fluorine-related precipitates, in which the fluorine is from the BF 2 + ion implantation. It is believed that the formation of substrate defects is the root cause of high junction leakage observed in the pMOSFET devices, and the leakage can be substantially reduced by 1-2 orders of magnitude with the extra high temperature anneal. On top of that, the distribution of the sheet resistance of the Ti-salicided p + -Si becomes tighter.

Stress-induced leakage currents of CMOS ULSI devices with shallow trench isolation

The correlation of MOSFET electrical characteristics to the levels of mechanical stress in STI structures used for the device manufacturing has been analyzed. The model of stress evolution during STI formation was developed based on the results of experimental measurements and computer simulations. Accordingly, STI processes creating different levels of stresses were designed and used to manufacture ULSI. Electrical parameters of a large variety of MOSFET devices were tested and weighted against the STI processes employed. This enabled the identification of the device leakage currents which resulted from high STI stress: the diode leakage dependent on isolation width, MOSFET standby currents dependent on active device width and gate bias, and the excessive leakage of field-edge-intensive devices. The first phenomenon was found to be associated with the incident of dislocations. The other kinds of leakage could reach critical levels even at moderate stress below the threshold for the onset of dislocation. According to the results of the device leakage characterization, critical stress states of STI structures can be readily monitored using conventional approaches of electrical testing. This provides an effective means for STI process and material integration and obtaining low stress dislocation-free structures.

Impact of boron penetration on gate oxide reliability and device performance in a dual-gate oxide process

The effect of boron penetration on device performance and gate oxide reliability of P+ polysilicon gate MOSFET of a dual oxide process with salicide block module was investigated. To get stable non-salicided poly sheet resistance, a capping oxide is required before source/drain RTA anneal. It is found that the transistor performance and gate oxide reliability were degraded with the capping oxide. The optimization scheme by replacing BF2 with Boron for P+ implant is demonstrated.

Analysis of N-channel transistor punch-through related to STI process

In this paper we study the causes of an unusually high N- channel transistor punch through leakage using a shallow trench isolation process. This resistive short between source and drain exhibits high structural dependence and has a strong dependence on the channel length and the total field edge of the device. Unlike the normal off-channel leakage. The leakage current of this resistive short shows weak dependence on temperature. Such a correlation between leakage and structure is examined for the first time in this paper. Experimentation with various trench liner oxidation schemes and gap-fill densification was the key to resolve the leakage.

Degradation of PMOS series resistance due to Si implantation for Ti-salicide process

Advanced Ti-Salicide schemes using Si implantation either before or after Ti deposition adversely affected transistor performance through lowering of the device drivability. Device impact was sen in increase of the pMOS series resistance with increasing per-amorphization implant Si implant energy. Likewise, the amount of amorphization and silicidation due to different as-deposited Ti thickness for the implant through metal scheme affected most adversely for the pMOS. This degradation is attributed to the implantation and silicidation induced generation of vacancies and interstitials, resulting in the de-activation and subsequent re-distribution of dopants around the transistor LDD and source/drain regions. Results were shown to conform with TRIM simulation of Si implantation profiles.

Impact of Silicon Wafer Material on Dislocation Generation in Local Oxidation

Crystalline quality of locally oxidized silicon wafers has been studied. Wafers from different supply sources were found to be differently susceptible to stress-induced dislocation generation, although they had been produced to the same specification. On the basis of the analysis of a depth distribution of the dislocations, critical resolved shear stress of dislocation movement in the bulk areas of the wafers was determined. It varied from about 1.65 to 5.12 MPa and correlated positively to the surface defect density. The results show that uncontrollable variations of bulk silicon properties may significantly influence the stress-induced defect nucleation on the surface of wafers during processing.