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Dive into the research topics where David Vigar is active.

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Featured researches published by David Vigar.


Applied Physics Letters | 2005

Effective channel length measurement of metal-oxide-semiconductor transistors with pocket implant using the subthreshold current-voltage characteristics based on remote Coulomb scattering

Chee-Wee Eng; W. S. Lau; David Vigar; S. S. Tan; L. Chan

For deep submicron metal-oxide-semiconductor (MOS) transistors with pocket implant, the electron mobility of the short channel transistor is always smaller than that of the long channel transistor in the above-threshold regime, resulting in serious error in effective channel length (Leff) measurement based on the assumption that the mobility is independent of gate length. Our theory predicts that when the gate oxide is very thin the electron mobility is approximately equal for short and long channel MOS transistors in the subthreshold regime. Thus it is possible to perform Leff measurement in the subthreshold region of MOS transistors with ultrathin gate oxide.


Japanese Journal of Applied Physics | 2003

An Improved Shift-and-Ratio Effective Channel Length Extraction Method for Metal Oxide Silicon Transistors with Halo/Pocket Implants

Chee-Wee Eng; W. S. Lau; David Vigar; James Yong Meng Lee

The original shift-and-ratio method tends to significantly over-estimate the effective channel length Leff of metal–oxide–silicon (MOS) transistors with halo/pocket implants because the carrier mobility of the short transistor tends to be smaller than that of the long transistor. A modification of the original method has been tested on both n-channel metal–oxide–silicon (NMOS) and p-channel metal–oxide–silicon (PMOS) transistors fabricated by state-of-the-art complementary metal–oxide–silicon (CMOS) technology. The values of Leff generated by this method are more reasonable than the original shift-and-ratio method with much less computation time involved. The theoretical basis of our method is that the carrier mobility of the short transistor is approximately equal to that of the long transistor when the gate voltage is close to the threshold voltage for state-of-the-art MOS transistors with <2 nm gate oxide.


International Symposium on Microelectronics and Assembly | 2000

Importance of oxide capping on the suppression of dopant outdiffusion for salicide block process

Hong Liao; Soh Yun Siah; David Vigar

In this paper, the effect of dopant out diffusion on unsalicided polysilicon resistance has been intensively investigated. It has been found that excessive dopant out diffusion as a result of non-optimized oxide capping could cause a large variation in sheet resistance of the unsalicided polysilicon resistor. For this salicide block process, great attention needs to be paid for the suppression of dopant out diffusion. Based on understanding of the cause of the inconsistent, unsalicided polysilicon resistance, we demonstrate an implementation of salicide blocking for 0.25 micrometers CMOS technology with a well controlled unsalicided polysilicon resistance by exploring the various process trade-offs in the choice of oxide for the salicide blocking and optimizing the subsequent thermal annealing process.


International Symposium on Microelectronics and Assembly | 2000

Impact of boron penetration on gate oxide reliability and device performance in a dual-gate oxide process

Yunqiang Zhang; Chock Hing Gan; Xi Li; James Yong Meng Lee; David Vigar; Ravi Sundaresan

The effect of boron penetration on device performance and gate oxide reliability of P+ polysilicon gate MOSFET of a dual oxide process with salicide block module was investigated. To get stable non-salicided poly sheet resistance, a capping oxide is required before source/drain RTA anneal. It is found that the transistor performance and gate oxide reliability were degraded with the capping oxide. The optimization scheme by replacing BF2 with Boron for P+ implant is demonstrated.


International Symposium on Microelectronics and Assembly | 2000

Analysis of N-channel transistor punch-through related to STI process

Yunqiang Zhang; James Yong Meng Lee; Chock Hing Gan; David Vigar; Ravi Sundaresan

In this paper we study the causes of an unusually high N- channel transistor punch through leakage using a shallow trench isolation process. This resistive short between source and drain exhibits high structural dependence and has a strong dependence on the channel length and the total field edge of the device. Unlike the normal off-channel leakage. The leakage current of this resistive short shows weak dependence on temperature. Such a correlation between leakage and structure is examined for the first time in this paper. Experimentation with various trench liner oxidation schemes and gap-fill densification was the key to resolve the leakage.


Archive | 2003

Method of forming double-gated silicon-on-insulator (SOI) transistors with corner rounding

Yong Meng Lee; Da Jin; David Vigar


Archive | 2003

Device, design and method for a slot in a conductive area

Patrick Tan; Kheng Chok Tee; David Vigar; Tat Wei Chua


Archive | 2003

Method of forming double-gate semiconductor-on-insulator (SOI) transistors

Yong Meng Lee; Da Jin; Mau Lam Lai; David Vigar; Siow Lee Chwa


Archive | 2004

Novel method to make corner cross-grid structures in copper metallization

Patrick Tan; Kheng Chok Tee; David Vigar


Archive | 2003

Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance

Yong Meng Lee; Da Jin; David Vigar

Collaboration


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Da Jin

Chartered Semiconductor Manufacturing

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Yong Meng Lee

Chartered Semiconductor Manufacturing

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Chee-Wee Eng

Nanyang Technological University

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James Yong Meng Lee

Chartered Semiconductor Manufacturing

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W. S. Lau

Nanyang Technological University

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Chock Hing Gan

Chartered Semiconductor Manufacturing

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Kheng Chok Tee

Chartered Semiconductor Manufacturing

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Lap Chan

Chartered Semiconductor Manufacturing

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Patrick Tan

Chartered Semiconductor Manufacturing

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Ravi Sundaresan

Chartered Semiconductor Manufacturing

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