Binwei Deng

The miniature optical transmitter and transceiver for the High-Luminosity LHC (HL-LHC) experiments

We present the design and test results of the Miniature optical Transmitter (MTx) and Transceiver (MTRx) for the high luminosity LHC (HL-LHC) experiments. MTx and MTRx are Transmitter Optical Subassembly (TOSA) and Receiver Optical Subassembly (ROSA) based. There are two major developments: the Vertical Cavity Surface Emitting Laser (VCSEL) driver ASIC LOCld and the mechanical latch that provides the connection to fibers. In this paper, we concentrate on the justification of this work, the design of the latch and the test results of these two modules with a Commercial Off-The-Shelf (COTS) VCSEL driver.

A line code with quick-resynchronization capability and low latency for the optical data links of LHC experiments

We propose a line code that has fast resynchronization capability and low latency. Both the encoder and decoder have been implemented in FPGAs. The encoder has also been implemented in an ASIC. The latency of the whole optical link (not including the optical fiber) is estimated to be less than 73.9 ns. In the case of radiation-induced link synchronization loss, the decoder can recover the synchronization in 25 ns. The line code will be used in the ATLAS liquid argon calorimeter Phase-I trigger upgrade and can also be potentially used in other LHC experiments.

Optical data transmission ASICs for the high-luminosity LHC (HL-LHC) experiments

We present the design and test results of two optical data transmission ASICs for the High-Luminosity LHC (HL-LHC) experiments. These ASICs include a two-channel serializer (LOCs2) and a single-channel Vertical Cavity Surface Emitting Laser (VCSEL) driver (LOCld1V2). Both ASICs are fabricated in a commercial 0.25-μm Silicon-on-Sapphire (SoS) CMOS technology and operate at a data rate up to 8 Gbps per channel. The power consumption of LOCs2 and LOCld1V2 are 1.25 W and 0.27 W at 8-Gbps data rate, respectively. LOCld1V2 has been verified meeting the radiation-tolerance requirements for HL-LHC experiments.

Component Prototypes Towards a Low-Latency, Small-Form-Factor Optical Link for the ATLAS Liquid Argon Calorimeter Phase-I Trigger Upgrade

This paper presents several component prototypes towards a low-latency, small-form-factor optical link designed for the ATLAS Liquid Argon Calorimeter Phase-I trigger upgrade. A prototype of the custom-made dual-channel optical transmitter module, the Miniature optical Transmitter (MTx), with separate transmitter optical sub-assemblies (TOSAs) has been demonstrated at data rates up to 8 Gbps per channel. A Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC has been developed and is used in the current MTx prototypes. A serializer ASIC prototype, operating at up to 8 Gbps per channel, has been designed and tested. A low-latency, low-overhead encoder ASIC prototype has been designed and tested. The latency of the whole link, including the transmitter latency and the receiver latency but not the latency of the fiber, is estimated to be less than 57.9 ns. The size of the MTx is 45 mm ×15 mm ×6 mm.

The clock distribution system for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade Demonstrator

A prototype Liquid-argon Trigger Digitizer Board (LTDB), called the LTDB Demonstrator, has been developed to demonstrate the functions of the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics upgrade. Forty Analog-to-Digital converters and four FPGAs with embedded multi-gigabit-transceivers on each Demonstrator need high quality clocks. A clock distribution system based on commercial components has been developed for the Demonstrator. The design of the clock distribution system is presented. The performance of the clock distribution system has been evaluated. The components used in the clock distribution system have been qualified to meet radiation tolerance requirements of the Demonstrator.

The 120Gbps VCSEL Array Based Optical Transmitter (ATx) development for the High-Luminosity LHC (HL-LHC) experiments

The integration of a Verticle Cavity Surface-Emitting Laser (VCSEL) array and a driving Application-Specific Integrated Circuit (ASIC) in a custom optical array transmitter module (ATx) for operation in the detector front-end is constructed, assembled and tested. The ATx provides 12 parallel channels with each channel operating at 10 Gbps. The optical transmitter eye diagram passes the eye mask and the bit-error rate (BER) less than 10(-12) transmission is achieved at 10 Gbps/ch. The overall insertion loss including the radiation induced attenuation is sufficiently low to meet the proposed link budget requirement.

JTAG-based remote configuration of FPGAs over optical fibers

In this paper, a remote FPGA-configuration method based on JTAG extension over optical fibers is presented. The method takes advantage of commercial components and ready-to-use software such as iMPACT and does not require any hardware or software development. The method combines the advantages of the slow remote JTAG configuration and the fast local flash memory configuration. The method has been verified successfully and used in the Demonstrator of Liquid-Argon Trigger Digitization Board (LTDB) for the ATLAS liquid argon calorimeter Phase-I trigger upgrade. All components on the FPGA side are verified to meet the radiation tolerance requirements.

Two low-power optical data transmission ASICs for the ATLAS Liquid Argon Calorimeter readout upgrade

Abstract A serializer ASIC and a VCSEL driver ASIC are needed for the ATLAS liquid argon calorimeter readout phase-I upgrade. The baseline ASICs are the serializer LOCx2 and the VCSEL driver LOCld, designed in a 0.25- μ m Silicon-on-Sapphire (SoS) CMOS technology. Based on a 130-nm CMOS technology, we design two pin-to-pin-compatible backup ASICs, LOCx2-130 and LOCld-130. Their power consumptions are much lower then their counterparts. We present the design of LOCx2-130 and LOCld-130. The test results of LOCx2-130 are also presented.

Low-latency and low-overhead encoder ASIC in the ATLAS LAr calorimeter trigger upgrade

ABSTRACT In this article, an encoder Application Specific Integrated Circuit (ASIC) for high-speed serial data transmission is presented. The ASIC implements a low-latency and low-overhead line code and is fabricated with a commercial 0.25-µm Silicon-on-Sapphire CMOS technology. The ASIC operates at 640 MHz with a latency of no greater than 6.25 ns and the overhead of 14.3%. The encoder will be integrated with a serialiser and will be used in the A Toroidal LHC ApparatuS Liquid Argon (LAr) calorimeter Phase-I trigger upgrade.

A 54-mW 8-Gbit/s VCSEL driver in a 65-nm CMOS technology

We report a VCSEL driver ASIC designed and fabricated in a commercial 65-nm CMOS process. At 8 Gbps, the eye diagram passes the eye mask test and the bit-error-rate is less than 10(-12) at the 95% confidence level. The total power consumption (including VCSEL) is about 54mW, less than 1/4 of our previous VCSEL driver ASIC in a silicon-on-sapphire CMOS technology. The VCSEL driver has been tested in a neutron beam with the maximum energy of 800MeV and the cross section has been estimated to be less than 3.14 x 10(-11) cm(2).